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Author Topic: Synchronising multiple DDS ICs (negative edge sync)  (Read 504 times)
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LithiumOverdosE
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« on: February 19, 2016, 08:09:08 20:09 »

I'm currently programming three AD9851 DDS ICs to work in sync but on different frequencies.
They're all commonly clocked with 30 MHz reference clock and have 6x multipliers enabled.

The programming part was easy but now I have to sync them all.

The sync procedure is pretty much straightforward timing-wise as described in AN-587 http://www.analog.com/media/en/technical-documentation/application-notes/AN-587.pdf

However, I'm using AD9851 internal 6x clock multiplier and I'm actually lacking the practical idea for negative edge triggering of FQ_UD pulse.
I considered using fast negative edge triggered J-K flip flop but I'm not sure how to limit duration of FQ_UD pulse because if the duration of the FQ_UD pulse is too long it gets interrupted and I end up with multiple pulses.

Does anyone have any advice how to effectively limit the duration of the resulting FQ_UD pulse so that it doesn't get repeated?
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optikon
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« Reply #1 on: February 19, 2016, 10:24:01 22:24 »

I dont completely follow your application intent, but my first thought its to take over the FQ_UD pulse and control it via FPGA state machine.
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Checksum8
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« Reply #2 on: February 19, 2016, 10:28:16 22:28 »

It sounds like you need a "one shot" circuit. A 74hc14 Schmitt trigger with a RC network on the input. What
frequency are you expecting to feed the FQ_UD pin?

Add: Analog Devices has a good forum where their application engineers actually try to help you out.
« Last Edit: February 19, 2016, 10:38:12 22:38 by Checksum8 » Logged
LithiumOverdosE
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« Reply #3 on: February 20, 2016, 12:52:57 00:52 »

@optikon

Thx for the idea but I'm using humble PIC 18F46K22 which is more than capable of handling all the tasks and FPGA seems like unnecessary overkill.

I just realised that I didn't mention which microcontroller I'm using. Sorry about that.



@Cheksum8

FQ_UD pin refresh rate is not important because sweeps or anything like it are not required.
Basically, it is used just once for syncing (common mode with all ICs FQ_UD operating together) and after that every FQ_UD pin is to be operated separately.
I was thinking of using fast logic gates (still weighing the options) to allow FQ_UD pins to work together and separately.
However, I'm still to solve the problem of negative edge sync pulse.

Thx for pointing out Analog Devices forum.
I missed that one but mostly because I find ppl here are quite helpful and creative. 
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Signal
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« Reply #4 on: February 21, 2016, 12:28:34 00:28 »

As I see in AN-587.pdf Figure 6 (Proper Timing Relationship Using the 6 Multiplier) all you need is a strict ns sync between REFCLOCK and FQ_UD signals. Then I'd use D-trigger and inverter, that is useful not only to invert clock for positive edge triggering but also for alignment of edges.
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PICker
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« Reply #5 on: February 21, 2016, 07:56:19 07:56 »

Did you think to use the internal analog comparator module of the 18F46K22?
Have a look to page 311-319 of the 18F46K22 datasheet:
http://ww1.microchip.com/downloads/en/DeviceDoc/41412F.pdf
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Signal
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« Reply #6 on: February 21, 2016, 11:39:30 11:39 »

Did you think to use the internal analog comparator module of the 18F46K22?
Have a look to page 311-319 of the 18F46K22 datasheet:
Have a look to page 444 of the 18F46K22 datasheet: TABLE 27-1, CM04-Response time: typical 200 ns,  max 400 ns.
Have a look to page 5 of the AD9851 application note AN-587: Table I. Setup Time Range between FQ_UD and REF CLK: from 8 ns to 1 ns.

18F46K22 has also SR-latch that is not applicable here too. Think about three 20 euro AD9851 chips and suggestion to use slow PIC peripheral for signal conditioning - for what?
Forgetting timing constraints I'm curious what circuit with analog comparator do you mean for required function?
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PICker
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« Reply #7 on: February 21, 2016, 12:33:55 12:33 »

from the LithiumOverdosE's post we do not know the required operating Freq range of his application (the AD9851 offers a wide range of input freqs).
If the range is (very)low, some funcs will be simulated via PIC firmware.
If the freq range is 30 MHz (6x multipliers enabled) is I agree with you, Signal, the 18F46K22 inner comparators react too slowly.


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LithiumOverdosE
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« Reply #8 on: February 21, 2016, 02:28:05 14:28 »

Well, my decision to use humble PIC is because I simply don't have a need for fast complex calculations.

The goal is to produce three independently controlled signals which are later to be fed into interconnected set of AM modulators and additional conditioning (I'm not exactly privy to what exactly is done at later stage).

PIC is there only to handle ordinary 20x4 LCD and two incremental encoders.
Calculation of tuning word is done with 1 Hz resolution with no sweeps or anything so the calc is quite fast and done entirely with integer math.
Programming interface is parallel because I have more enough available pins.

Currently, a single PIC easily handles three AD9851 run from the same clock.
However, the sync is sometimes a bit off and I cannot simply correct it by correcting the phase due to relatively low resolution of only 5 bits (11.25 per step).

So, while more complex functionality would require faster processor in this case it would be a major overkill because the "only" real problem is syncing of multiple AD9851 working with 6x multiplier (180 Mhz).

The main challenge is proper timing due to requirements for AD9851 that uses 6x multiplier at 5V and with REFCLK of 30 MHz.
In particular, maximal delay between negative edge of REFCLK and FQ_UD rising edge have to be less than 2ns.
I considered a solution similar to what Signal proposed but with using several inverters (or additional flip-flop and inverter) as a sort of a delay line to allow for flip-flop to change its output.
While the solution may work it would depend greatly on which families of logic ICs are used for flip-flop and which are used for inverters and to complicate things further their specs also vary between different manufacturers.

Additional possible problem is the length of the FQ_UD impulse because it would likely last more than several clocks of REFCLK so it would be activated several times in succession.
In this regard data sheet is not clear on what would happen because it only states:
Quote
The rising edge of FQ_UD transfers the contents of the register into the device to be acted upon and resets the word address pointer to W0. Subsequent W_CLK rising edges load 8-bit data, starting at W0 and then move the word pointer to the next word. After W0 through W4 are loaded, additional W_CLK edges are ignored until either a RESET is asserted or an FQ_UD rising edge resets the address pointer to W0 in preparation for the next 8-bit load.

So, the content of the input register would remain intact.
However the entire procedure lasts 18 REFCLK cycles which means it would get interrupted by multiple FQ_UD pulses.
The data sheet don't clearly state if the internal processes can be interrupted and reset during those 18 REFCLK cycles.
If it is possible then it wouldn't matter if several FQ_UD pulses were issued because the end result would be correct sync and intermittent losses of signal during frequency corrections are of no concern in this particular case.

There are still many unknowns but it is always a good thing to hear other opinions and suggestions.




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PICker
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« Reply #9 on: February 21, 2016, 03:38:42 15:38 »

If you have the possibility to switch from 18F46K22 to another MCU and you need more DAC resolution, you could have a look to other low cost PICs ie:
http://www.microchip.com/wwwproducts/en/PIC16F1787
http://www.microchip.com/wwwproducts/en/PIC16F1788
http://www.microchip.com/wwwproducts/en/PIC16F1789

or the new parts:
http://www.microchip.com/wwwproducts/en/PIC16F1777
http://www.microchip.com/wwwproducts/en/PIC16F1778
http://www.microchip.com/wwwproducts/en/PIC16F1779
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LithiumOverdosE
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« Reply #10 on: February 22, 2016, 11:13:42 11:13 »

Thx for the information but why would I need DAC to drive AD9851?
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PICker
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« Reply #11 on: February 22, 2016, 03:48:36 15:48 »

Hi, LithiumOverdosE,
I've confused the "relatively low resolution of only 5 bits" of your last post, obviously referred to  the phase-modulation correction factor of the AD9851 with the 5-bit DAC of  the 18F46K22. I'm actually using a PIC16F1789, selected just for its 8-bit DAC.
I'm sorry for this misunderstanding.
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