Well, my decision to use humble PIC is because I simply don't have a need for fast complex calculations.
The goal is to produce three independently controlled signals which are later to be fed into interconnected set of AM modulators and additional conditioning (I'm not exactly privy to what exactly is done at later stage).
PIC is there only to handle ordinary 20x4 LCD and two incremental encoders.
Calculation of tuning word is done with 1 Hz resolution with no sweeps or anything so the calc is quite fast and done entirely with integer math.
Programming interface is parallel because I have more enough available pins.
Currently, a single PIC easily handles three AD9851 run from the same clock.
However, the sync is sometimes a bit off and I cannot simply correct it by correcting the phase due to relatively low resolution of only 5 bits (11.25° per step).
So, while more complex functionality would require faster processor in this case it would be a major overkill because the "only" real problem is syncing of multiple AD9851 working with 6x multiplier (180 Mhz).
The main challenge is proper timing due to requirements for AD9851 that uses 6x multiplier at 5V and with REFCLK of 30 MHz.
In particular, maximal delay between negative edge of REFCLK and FQ_UD rising edge have to be less than 2ns.
I considered a solution similar to what Signal proposed but with using several inverters (or additional flip-flop and inverter) as a sort of a delay line to allow for flip-flop to change its output.
While the solution may work it would depend greatly on which families of logic ICs are used for flip-flop and which are used for inverters and to complicate things further their specs also vary between different manufacturers.
Additional possible problem is the length of the FQ_UD impulse because it would likely last more than several clocks of REFCLK so it would be activated several times in succession.
In this regard data sheet is not clear on what would happen because it only states:
The rising edge of FQ_UD transfers the contents of the register into the device to be acted upon and resets the word address pointer to W0. Subsequent W_CLK rising edges load 8-bit data, starting at W0 and then move the word pointer to the next word. After W0 through W4 are loaded, additional W_CLK edges are ignored until either a RESET is asserted or an FQ_UD rising edge resets the address pointer to W0 in preparation for the next 8-bit load.
So, the content of the input register would remain intact.
However the entire procedure lasts 18 REFCLK cycles which means it would get interrupted by multiple FQ_UD pulses.
The data sheet don't clearly state if the internal processes can be interrupted and reset during those 18 REFCLK cycles.
If it is possible then it wouldn't matter if several FQ_UD pulses were issued because the end result would be correct sync and intermittent losses of signal during frequency corrections are of no concern in this particular case.
There are still many unknowns but it is always a good thing to hear other opinions and suggestions.