Walkura has an important point. There are no snubbers to supress the leakage inductance fly-back. High dv/dt will in all likelihood trigger the SCR's as Walkura mention and destroy the MOSFETs. Even if the SCR's were removed the snubbers would still be needed. This means this circuit is not a real design.
That said, academically the SCR's seem to provide two functions, time delay to avoid shoot-through and the bulk of the heat dissipation losses.
Shoot-through is where both MOSFETs and SCRs are overlapping conduction causing large currents in the devices and the transformer. Sharing dissipation losses allows great currents to be handled without over heating the MOSFETs (more later on this).
The SCR's will not trigger until their cathodes are below 9 volts (+12v-Vbe-Dfv-Vgt: driver supply voltage, less the transistor Vbe, less the forward voltage of the in series gate diode and the SCR minimum gate turn on voltage). This provides both the delay to avoid shoot-through and for the SCR to take the brunt of the turn-on losses.
Normally shoot-through would be avoided in the MOSFET driver design, typically a S-R flip-flop to provide a dead-time.
I've designed SMPS circuit for many years and I've never seen this SCR arrangement before, normally one would avoid conductive losses in the power flow path when ever possible. The SCR's Vtm is 1.9V at 100A. This would not be so bad if the supply voltage where several hundred volts and the currents rather small, but this half bridge is only +24V and large currents. Compare the SCR conductive losses to the IRFP064 ... 9mOhms at Id=78A! Seems the MOSFETs are much better than the SCR's! This causes one to really wonder what the designer was thinking ... or not thinking
It appears that it was intended for the MOSFETs to provide SCR commuting only and not much else! Likely as well, shoot-through was never considered. Not much to learn here!