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Author Topic: PWM based inverter for Grid tied applications using AVR  (Read 2262 times)
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drthilina
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« on: May 10, 2009, 08:29:46 20:29 »

Dear all,
 I'm trying to develop a PWM based inverter and like to share my development with you all. I would really appreciate if you can share your thoughts about the application..

Many thanks
drthilina

Posted on: May 10, 2009, 08:07:11 20:07 - Automerged

First of all the project plan....
assuming the hardware part is not a problem...

the analog circuits will detect the rising edge of the sine wave and a interrupt is created in ATmega8 which is clocked and 6MHz. Internal timer2 will keep track of the timing of the period of the AC sine wave. A sine wave lookup table is used to convert the angle value to amplitude and it is given to the PWM to drive inverse parallel Transistors...

here is the code:

#include <avr/io.h>
#include <avr/pgmspace.h>
#include <avr/interrupt.h>


unsigned char TMR2_overflow=0;
unsigned int index=0;
unsigned char positive_cycle_sine_wave[1080] PROGMEM={0,4,9,13,18,22,27,31,35,40,44,49,53
,57,62,66,70,75,79,83,87,91,96,100,104,108,112,116,120,124,128,131,135,139,143,146,150,153
,157,160,164,167,171,174,177,180,183,186,190,192,195,198,201,204,206,209,211,214,216,219
,221,223,225,227,229,231,233,235,236,238,240,241,243,244,245,246,247,248,249,250,251,252
,253,253,254,254,254,255,255,255,255,255,255,255,254,254,254,253,253,252,251,250,249,248
,247,246,245,244,243,241,240,238,236,235,233,231,229,227,225,223,221,219,216,214,211,209
,206,204,201,198,195,192,190,186,183,180,177,174,171,167,164,160,157,153,150,146,143,139
,135,131,128,124,120,116,112,108,104,100,96,91,87,83,79,75,70,66,62,57,53,49,44,40,35,31
,27,22,18,13,9,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
,0,0,0,0,0,0,0,0,0,4,9,13,18,22,27,31,35,40,44,49,53,57,62,66,70,75,79,83,87,91,96,100,104
,108,112,116,120,124,128,131,135,139,143,146,150,153,157,160,164,167,171,174,177,180,183
,186,190,192,195,198,201,204,206,209,211,214,216,219,221,223,225,227,229,231,233,235,236
,238,240,241,243,244,245,246,247,248,249,250,251,252,253,253,254,254,254,255,255,255,255
,255,255,255,254,254,254,253,253,252,251,250,249,248,247,246,245,244,243,241,240,238,236
,235,233,231,229,227,225,223,221,219,216,214,211,209,206,204,201,198,195,192,190,186,183
,180,177,174,171,167,164,160,157,153,150,146,143,139,135,131,128,124,120,116,112,108,104
,100,96,91,87,83,79,75,70,66,62,57,53,49,44,40,35,31,27,22,18,13,9,4,0,0,0,0,0,0,0,0,0,0
,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,4,9,13,18
,22,27,31,35,40,44,49,53,57,62,66,70,75,79,83,87,91,96,100,104,108,112,116,120,124,128,131
,135,139,143,146,150,153,157,160,164,167,171,174,177,180,183,186,190,192,195,198,201,204
,206,209,211,214,216,219,221,223,225,227,229,231,233,235,236,238,240,241,243,244,245,246
,247,248,249,250,251,252,253,253,254,254,254,255,255,255,255,255,255,255,254,254,254,253
,253,252,251,250,249,248,247,246,245,244,243,241,240,238,236,235,233,231,229,227,225,223
,221,219,216,214,211,209,206,204,201,198,195,192,190,186,183,180,177,174,171,167,164,160
,157,153,150,146,143,139,135,131,128,124,120,116,112,108,104,100,96,91,87,83,79,75,70,66
,62,57,53,49,44,40,35,31,27,22,18,13,9,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};

int main(void)
{
   // Set PORTB as output
   DDRB=255;
   DDRC=254;
   DDRD=0xFB;

   ADMUX=(0<<REFS1)+(0<<REFS0)+(1<<ADLAR)//ADref on pin AREF, results left justified
   +(0<<MUX3)+(0<<MUX2)+(0<<MUX1)+(0<<MUX0);//Channel 0 selected
   ADCSRA=(1<<ADEN)+(0<<ADSC)+(0<<ADFR)+(0<<ADIE)//AD enabled and not free running
   +(1<<ADPS2)+(0<<ADPS1)+(0<<ADPS0);//Division factor of 16


   TCCR2=(0<<CS22)+(1<<CS21)+(0<<CS20);//Timer2 ON and prescalling
   OCR2=15;//compare to generate interrupt flag
   TIMSK=(1<<OCIE2);//Timer2 interrupt request is enabled

   TCCR1A=(1<<COM1A1)+(0<<COM1A0)+(1<<COM1B1)+(0<<COM1B0)//OC1A AND 0C1B are set low on match
   +(0<<WGM11)+(1<<WGM10);// phase correct PWM 8-bit
   TCCR1B=(0<<ICNC1)+(0<<ICES1)+(0<<WGM13)+(0<<WGM12)//phase correct PWM 8-bit
   +(0<<CS12)+(0<<CS11)+(1<<CS10);//clock prescaling

   MCUCR=(1<<ISC01)+(1<<ISC00);//Interrupt on rising edge
   GICR=(1<<INT0);//External interrupt 0 enabled
   SREG|=(1<<7);//Enable global interrupt
   while(1)
   {
      static unsigned int temp;

      temp=index/2+360+9+ADCH/2-64;
      OCR1AL=pgm_read_byte(&positive_cycle_sine_wave[temp]);//PWM on TIMER1 on PIN OC1A
      temp=temp+180;
      OCR1BL=pgm_read_byte(&positive_cycle_sine_wave[temp]);//PWM on TIMER1 on PIN OC1B
      ADCSRA|=(1<<ADSC);
      while(TMR2_overflow==0);
      TMR2_overflow=0;
   }
}

//------------------------------------------------------
ISR(INT0_vect)
{
   index=0;
}
//------------------------------------------------------
ISR(TIMER2_COMP_vect)
{
   TMR2_overflow=1;
   TCNT2=0;
   index++;
   if(index>720)
   {
      index=0;
   }
}

Posted on: May 10, 2009, 08:13:10 20:13 - Automerged

heres the VSM circuit and is outputs
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