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December 04, 2016, 05:21:04 17:21


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Author Topic: Implement filter in verilog  (Read 351 times)
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promach
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« on: March 09, 2016, 12:39:28 00:39 »

Dear all verilog seniors.

I am doing a small project to design an image filter in verilog.

The image filter can be summarized in this picture:


I have the following filter equation


h[ i][j] = A*h[i-1][j-1] + B*h[ i][j-1] + C*h[i+1][j-1] + D*h[i-1][j] + E*h[ i][j] + F*h[i+1][j] + G*h[i-1][j+1] + H*h[ i][j+1] + I*h[i+1][j+1]


However, I have no prior knowledge in RTL/verilog.


How should I proceed ?
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hate
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« Reply #1 on: March 11, 2016, 12:35:47 12:35 »

Where do you plan to store your image?
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Gallymimu
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« Reply #2 on: April 03, 2016, 04:19:07 04:19 »

he doesn't need to store the image, he just needs to work on 9 pixels at a time.  That is of course assuming he has a front end that can stream the correct 6 pixels for each calculation, otherwise he'll need external ram to store the whole thing and then address the 9 pixels he needs each calculation.

It shouldn't be an issue either way really as external memory access is basically off the shelf.

one approach, assuming that the image comes in serial streamed left to right row by row is:
take serial stream to store bitmap in memory
access memory for 9 pixels needed, produce calc,
store each calculated pixel to another bitmap.

there of course isn't enough information to offer any significant help.  the problem is not well specified and everyone is going to be guessing.
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