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ASIC_GUY
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« on: April 12, 2012, 04:36:09 16:36 »

CountryCroles France
Sitenil
Note•   Working in the Backend team of Digital Logic sub-group, TR&D dept.

•   Project Title: Design and Development of Standard cell and ECL libraries
•   Details of Work done so far:

   Made LAYOUTS for cells like AND, OR, NAND, NOR, AO, INV, BF, DLY, DFlipflop, Schmitt trigger for following Standard cell libraries in Virtuoso & did their Physical verification using Caliber
•   BCD9S in 130 nm
•   CMOS32 16T GO2
•   CMOS 32 8T
•   FOURTUNE65LPLVT
•   CMOSM10ULP
   Exercised RTL-to-GDS flow for Non-retriggerable Mono-shot and an Up-Counter using Design Compiler  and IC Compiler
   Exercised ADE and ran pre-layout and post-layout Simulations on cells like Schmitt trigger, Delay, D flip-flop, Invertor using ELDO
   Exercised SKILL scripts to generate
•   TOPCELL of libraries so as to clear DRC, SRD and LVS, ABUT errors.
   Developed Shell Scripts to automate Regression
•   Library download from UPT(repository), creating their ALLCELL and running DRC, LVS on them
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