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Author Topic: [Req] Invite myvision_2525  (Read 434 times)
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myvision_2525
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« on: March 27, 2010, 11:28:44 11:28 »

CountryUSA
Sitenil
NoteHello,

Job Title: Digital Design and Verification Engineer,

Expertise in C, C++, Verilog, VHDL, System Verilog.

I was Teaching Assistant Digital System Design Lab. My responsibility include to helped professor to setup digital design lab for students, handled lab on RTL level coding using Verilog HDL/VDHL language, place and route on Xilinx ISE and implemented the design on Xilinx Spartan3E board, assisted students to understand design & simulation on CAD tool like Xilinx, ModelSIM, and Synopsys.

I also done my Master project on 16-bit Microprocessor using Speculative Tomasulo Algorithm, PCI express protocol, 2D Graphics FIR filter using Verilog and VHDL. I also gained immense knowledge by developing, integrating and testing an 8-by-8 ATM Switch using System Verilog.

I am sure that my higher education with an extensive project work, work experience, technical knowledge, and personal skills would be helpful to this forum.

Thank You.
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