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Author Topic: [Req] Invite smart_techie  (Read 439 times)
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smart_techie
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« on: November 18, 2009, 04:36:41 16:36 »

CountryINDIA
Sitenil
Note-> Working with mixed signal FPGAs. Design and implemetation of RTL modules for communication Protocols.

-> Interested in ASIC Design and implementation issues, could participate in discussions and share various Design , simulation , synthesis and verification tools.
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janakfun
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« Reply #1 on: November 18, 2009, 07:17:34 19:17 »

can you please brief out  what communication Protocols have you implemented till date ?
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Regards,

Janak
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