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Author Topic: full adder 4-bit schematic in Xilinx9.1  (Read 1398 times)
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diamadiss
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« on: May 09, 2009, 01:13:52 13:13 »

Hi to everyone. Iwant  help to working out a problem who i have. I desing a parallel full adder scematic in program Xilinx 9.1, and i have that problem. If my carry(C0 Cin) is '1' the addition is OK, but if my carry (C0 Cin) is 'o', the addition is wrong because i have wrong childe. Thanks for patient.Wink

I upload my project here :
http://www.sendspace.com/file/eowqgn
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INeedToLiveLonger
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« Reply #1 on: January 16, 2010, 05:23:40 17:23 »

Hi.
Post PDF of image of schematics.
I will tell you whats wrong in schematic.
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