i want to load axf image on dram...

[pamkmitnb]

i use fpga board with arm926ej-s core.
i wnat to load axf image on dram.
when i try it, "out of heap memory" message is printed.

plese, let me know what's problem on my code.

i'm using RVDebugger ,
dram base add: 0x60000000

Makefile... command line...

LFLAGS_DRAM = --ro-base 0x60000000 --first $(INIT)(Init) --entry $(INIT)(Init)

init.s ...below..
---------------------------------------------------------------------------------------------------------------
;IMPORT __use_no_semihosting_swi
PRESERVE8

;/* Exception Vectors */
AREA Init,CODE,READONLY
ENTRY

B ResetHandler
B .
B .
B .
B .
B .
B IrqHandlerDispatcher
B .

;/* Reset Handler */
ResetHandler
BL InitSmc
BL InitStackRegs

; If you want to use the C library, you should do either of
; 1. using '__main'
; 2. using '__rt_entry' and initializing RW/ZI manually

IMPORT __main
BL __main

;IMPORT __rt_entry
;BL InitCVar
;BL __rt_entry

;/* Dispatch to their own handler */
IMPORT IrqHandler
IrqHandlerDispatcher
STMFD sp!,{r0-r12,lr}
LDR r1,=IrqHandler
MOV lr,pc
MOV pc,r1
LDMFD sp!,{r0-r12,lr}
SUBS pc,lr,#4

;/* Initialize RW/ZI Area
; * If __main() is used, do not call this function.
; * Initialization is done in __main().
; */
IMPORT |Image$$RO$$Limit|
IMPORT |Image$$RW$$Base|
IMPORT |Image$$ZI$$Base|
IMPORT |Image$$ZI$$Limit|
InitCVar
LDR r0,=|Image$$RO$$Limit|
LDR r1,=|Image$$RW$$Base|
LDR r2,=|Image$$ZI$$Base|

CMP r0,r1
BEQ %F2
1
; Copy init data
CMP r1,r2
LDRCC r3,[r0],#4
STRCC r3,[r1],#4
BCC %B1
2
; Top of zero init segment
LDR r1,=|Image$$ZI$$Limit|
MOV r3,#0
3
; Zero init
CMP r2,r1
STRCC r3,[r2],#4
BCC %B3

; return
MOV pc,lr

;/* Set SROM(SRAM) Control Registers */
SROMBW EQU 0x40C20000
SROMBC0 EQU 0x40C20004
SROMBC1 EQU 0x40C20008
SROMBC2 EQU 0x40C2000C

InitSmc
; For MC4 demo, the timing values should be 0x100.
; Otherwise it makes errors. (Sean 7/17)

; Bank2=nBE/noWait/16bit
; Bank1=nBE/noWait/16bit
; Bank0=nBE/noWait/16bit
LDR r0,=SROMBW
LDR r1,=0x16d
STR r1,[r0]

; Bank0 Control (Tacc=3clk, maximum HCLK = 30 Mhz)
LDR r0,=SROMBC0
LDR r1,=0x100
STR r1,[r0]

; Bank1 Control (Tacc=3clk)
LDR r0,=SROMBC1
LDR r1,=0x100
STR r1,[r0]

; Bank2 Control (Tacc=3clk)
LDR r0,=SROMBC2
LDR r1,=0x100
STR r1,[r0]

; Return
MOV pc,lr

;/* Stack initialize */
USERMODE EQU 0x10
FIQMODE EQU 0x11
IRQMODE EQU 0x12
SVCMODE EQU 0x13
ABORTMODE EQU 0x17
UNDEFMODE EQU 0x1b
MODEMASK EQU 0x1f
NOINT EQU 0xc0

InitStackRegs
MRS r0,cpsr
BIC r0,r0,#MODEMASK
ORR r1,r0,#UNDEFMODE|NOINT
MSR cpsr_cxsf,r1
LDR sp,=UndefStackSt

ORR r1,r0,#ABORTMODE|NOINT
MSR cpsr_cxsf,r1
LDR sp,=AbortStackSt

ORR r1,r0,#IRQMODE|NOINT
MSR cpsr_cxsf,r1
LDR sp,=IrqStackSt

ORR r1,r0,#FIQMODE|NOINT
MSR cpsr_cxsf,r1
LDR sp,=FiqStackSt

ORR r1,r0,#SVCMODE|NOINT
MSR cpsr_cxsf,r1
LDR sp,=SvcStackSt

MOV pc,lr

;/* Stack & Heap */

; Because the 'One memory region' model is used
; the seperate heap region is not defined. (Sean)
EXPORT SvcStackSt
EXPORT SvcStackEnd
ALIGN
AREA Stacks,NOINIT
FiqStackEnd SPACE 0x0
FiqStackSt
IrqStackEnd SPACE 0x1000
IrqStackSt
AbortStackEnd SPACE 0x0
AbortStackSt
UndefStackEnd SPACE 0x0
UndefStackSt
SvcStackEnd SPACE 0x9000
SvcStackSt
UserStackEnd SPACE 0x0
UserStackSt

END
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