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Title: Problem Xilinx XC3S400 Configuration Post by: omidsht on June 02, 2011, 08:25:58 20:25 Hi
I have made a pcb board of the attached schematic, but I it has a problem. When I program the FPGA (xc3s400) solely through jtag (Platform cable usb II) the FPGA is program and okay, also when I program the FLASH (xcf04s) solely it is programmed as well (as impact says), but the problem is this that after programming the FLAHS, the FPGA is not configured and programmed by FLASH through master serial mode! as I check the DONE pin of FPGA, it never comes high ( it is low, indicating that FPGA has not been configured by FLASH), also the CCLK pin of FPGA continues to pulsing the CLK pin of FLASH for ever! I checked every thing but I couldnt find out what is the problem . I would be very thankfull if somebody can help me solving this problem thanks in advance Regards Title: Re: Problem Xilinx XC3S400 Configuration Post by: fpgaguy on June 06, 2011, 08:11:40 20:11 review http://www.xilinx.com/support/documentation/user_guides/ug332.pdf, page 58
probe cclk to see if you are seeing any clock distortion AT the prom pin Or try setting the "configrate" on the bitstream generator to something slower see: ConfigRate: Bitstream Option for CCLK For Master configuration mode, the ConfigRate bitstream generator option defines the frequency of the internally-generated CCLK oscillator. The actual frequency is approximate due to the characteristics of the silicon oscillator and varies by up to 50% over the temperature and voltage range. On Spartan-3E and Extended Spartan-3A family FPGAs, the resulting frequency for every ConfigRate setting is fully characterized and specified in the associated FPGA family data sheet. At power-on, CCLK always starts operation at its lowest frequency. Use the ConfigRate option to set the oscillator frequency to one of the other values shown in Table 2-8. Set this option graphically in “ISE Software Project Navigator,” page 42, as shown in Step 7 in Figure 1-7, page 44. The FPGA does not start operating at the higher CCLK frequency Title: Re: Problem Xilinx XC3S400 Configuration Post by: omidsht on June 08, 2011, 05:24:57 17:24 Hi, I checked what you said, every thig is okay , but still not working.
I have mentioned more details in the following address , please have a look http://forums.xilinx.com/t5/Spartan-Family-FPGAs/problem-in-my-designed-board/td-p/155438 regards |