PM3295
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« on: July 22, 2018, 10:24:35 22:24 » |
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I want to generate 44100 Hz from a 10 MHz clock input. What will be the best method to use to obtain this division with the lowest possible jitter?
Somebody suggested using an FPGA. Will that be possible? Not my area of expertise unfortunately.
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Vineyards
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« Reply #1 on: July 22, 2018, 11:07:08 23:07 » |
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I think what you need is a CMOS divider or prescaler like 4040, 4020, 4060 etc. Check out their specs. Sometimes it may also be necessary to use a suitable buffer or a voltage scaler circuit.
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h0nk
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« Reply #2 on: July 22, 2018, 11:11:06 23:11 » |
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Hello,
with a little PIC with a NCO (1503) you may get:
10e6 / 16 / 8 = 78125
44100 / 78125 * 65536 = 36994
36994/65536 * 78125 = 44,100.2845764 Hz
Good enough?
Best Regards
P.S.: Put a 4046 PLL behind the NCO to clear out the jitter.
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« Last Edit: July 22, 2018, 11:18:10 23:18 by h0nk »
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solutions
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« Reply #3 on: July 23, 2018, 10:05:39 10:05 » |
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Depends on the 10MHz source/reference, what your specs are for the 44.1kHz, whether you are after jitter on the clock or the data, and what you are doing with said 44.1kHz.
You'll get crap solutions suggested here, and nothing but guesses, because you haven't provided much info at all on the application and its constraints
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PM3295
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« Reply #4 on: July 23, 2018, 04:26:25 16:26 » |
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The eventual goal is to generate very stable (low jitter) frequencies to be used for various common audio-sampling clock frequencies. The 10 MHz reference will typically be coming from an OCXO, either sine or square wave. The frequencies I want to derive will be 44100, 48000, 88200 and 96000 Hz. It will be great if the output frequency can be made selectable. For this reason it was suggested that an FPGA may be the best solution? I hope it gives a better idea of my requirement.
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vern
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« Reply #5 on: July 23, 2018, 05:32:40 17:32 » |
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Why don't you take a 14.112MHz quartz / oscillator? You can generate any of the above frequencies from it with a simple divider / counter, without jitter
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PM3295
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« Reply #6 on: July 23, 2018, 06:06:34 18:06 » |
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I appreciate that it would be possible using a custom crystal or oscillator frequency as you suggested, but I wonder how easy it will be to obtain? High performance 10 MHz oscillators are readily available on the used market at economical pricing.
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Signal
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« Reply #7 on: July 23, 2018, 06:33:13 18:33 » |
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MK2703B PLL AUDIO CLOCK SYNTHESIZER, SOIC-8, 27MHz to 8.192, 11.2896, 12.288 or 24.576 MHz https://www.idt.com/document/dst/mk2703b-datasheetPosted on: July 23, 2018, 08:18:16 20:18 - Automerged
I'd sought not FPGA but rather a specialized solution. To get audio clocks is not an unique task, so there should be plenty of generators/synthesizers standalone or integrated in codecs. PLL170x yet another.
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h0nk
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« Reply #8 on: July 23, 2018, 07:48:34 19:48 » |
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Some years ago, i built a digital audio converter with the CS8401 and a CS8412. I had no difficulties to get matching crystals for 44.100 kbps and 48.000 kbps: 22.579 MHz and 24.576 MHz. The datasheet (CS8412) specifies the clocks as: 44.1 kHz +- 400 ppm and 48 kHz +- 400 ppm.
Best Regards
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Sideshow Bob
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« Reply #9 on: July 23, 2018, 08:29:25 20:29 » |
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Audio data converters in such applications are often Delta-Sigma, modulator-based devices that can over-sample the signal by a factor of up to 512, resulting in a system clock of 22.5792 MHz or 24.5760 MHz Edit If you are on a budget but blessed with a lot spare time go parts hunting in discarded pc equipment. It should no be hard to find a 22.5792 MHz or 24.5760 MHz crystal. And of course EBAY or Alibaba will have parts
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« Last Edit: July 23, 2018, 09:11:45 21:11 by Sideshow Bob »
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vern
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« Reply #10 on: July 23, 2018, 09:19:32 21:19 » |
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PM3295
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« Reply #11 on: July 23, 2018, 09:43:49 21:43 » |
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I want to thank all members for their valuable input and information. It opens a lot more possibilities for me to consider. I will certainly look into these and any other suggestions that may be applicable.
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M@X77
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« Reply #12 on: August 07, 2018, 09:40:49 09:40 » |
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And if use a mcu? 10Mhz is the clock, and use internal counter to divide it to necessary frequency
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vern
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« Reply #13 on: August 08, 2018, 08:28:28 08:28 » |
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M@X77, with a 10MHz clock you can have 44.247kHz or 44.052kHz because 10MHz divided by 44.100kHz does not give you an integer value
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debugasm
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« Reply #14 on: August 08, 2018, 09:52:31 09:52 » |
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With FPGA you can use NCO with large accumulator but since there is no whole divisor there will always be a small error. You can use the frequency of 44100 * 256 = 11289600 Hz for maximum precision and phase noise example this. For NCO you can use attached to calculate an NCO. N (nco) = (Fout * 2^n) / clk Fout = (clk / 2^n) * N (nco)
With precision of 24 bit step is 0,5960464477539062500000000 Hz With precision of 32 bit step is 0,0023283064365386962890625 Hz With precision of 40 bit step is 0,0000090949470177292823791 Hz With precision of 48 bit step is 0,0000000355271367880050092 Hz
With precision of 24 bit frequency output is 44100,2845764160 Hz clock error 0,0006452938313966 % With precision of 32 bit frequency output is 44100,0005230308 Hz clock error 0,0000011860108702 % With precision of 40 bit frequency output is 44099,9999955238 Hz clock error 0,0000000101501133 % With precision of 48 bit frequency output is 44100,0000000002 Hz clock error 0,0000000000004535 %
Good NCO ... debugasm
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