Sonsivri
 
*
Welcome, Guest. Please login or register.
Did you miss your activation email?
December 08, 2016, 10:45:37 10:45


Login with username, password and session length


Pages: [1]
Print
Author Topic: Learning to design DDR  (Read 890 times)
0 Members and 1 Guest are viewing this topic.
promach
Junior Member
**
Offline Offline

Posts: 43

Thank You
-Given: 14
-Receive: 0


« on: May 07, 2016, 02:27:50 02:27 »

Hi, I am student in my semester break period.

I want to take this time to learn about DDR internal design.

I search online but I could not get relevant design materials or courses.

Any ideas?

Logged
Unhappy
V.I.P
Active Member
*****
Offline Offline

Posts: 200

Thank You
-Given: 369
-Receive: 52


« Reply #1 on: May 08, 2016, 10:35:44 10:35 »

Hi, I am student in my semester break period.

I want to take this time to learn about DDR internal design.

I search online but I could not get relevant design materials or courses.

Any ideas?




what's DDR???
Logged
UncleBog
Junior Member
**
Offline Offline

Posts: 86

Thank You
-Given: 107
-Receive: 136


« Reply #2 on: May 08, 2016, 03:57:56 15:57 »

On the Assumption that you're referring to Double Data Rate; this is when data is driven / sampled on both edges (rising and falling) of the clock rather than just one edge per cycle. DDR has become synonymous with first generation DDR SDRAM which uses this method. Search for Altera C51010-1.2 for a more complete description.
Logged
promach
Junior Member
**
Offline Offline

Posts: 43

Thank You
-Given: 14
-Receive: 0


« Reply #3 on: May 09, 2016, 07:47:23 07:47 »

So, it would mean it is diffficult to find DDR internal design materials in the public domain in the net ?
Logged
UncleBog
Junior Member
**
Offline Offline

Posts: 86

Thank You
-Given: 107
-Receive: 136


« Reply #4 on: May 09, 2016, 11:16:41 11:16 »

DDR is a simple concept that I described in one sentence in my last email. By search I meant just google search for Altera C51010-1.2.

I've put a link to the Altera document describing DDR transmission in the attached file.

For a description of DDR SDRAM see Wikipedia.
Logged
roscoe
Newbie
*
Offline Offline

Posts: 7

Thank You
-Given: 3
-Receive: 2


« Reply #5 on: October 01, 2016, 02:30:33 02:30 »

If you want to see how the memory works internally, you can grab a behavioral model from one of the memory vendors (Micron, Samsung, Hynix, etc.)
Sometimes they are sent encrypted, but with a little effort, this can be overcome.

If you're concerned about layout type of things -- DDR layout is not all that it's made out to be.  You have quite a bit of trace length, even at higher clock rates, before length matching will generally matter.  It's a bigger deal with DIMMs than with discrete components.
Logged
bigtoy
Active Member
***
Offline Offline

Posts: 152

Thank You
-Given: 127
-Receive: 197


« Reply #6 on: October 01, 2016, 07:44:33 19:44 »

Pick up the app notes for any processor or other device which support DDR RAM and they'll tell you what's required. A few years ago I did a design using a TI Sitara processor (ARM Cortex A8) and they show you what to do - the midpoint terminations and so forth. We did trace length matching on that board just because we could, but I agree with roscoe it's not always necessary. But, putting some margin into a design is usually a good idea.
Logged
roscoe
Newbie
*
Offline Offline

Posts: 7

Thank You
-Given: 3
-Receive: 2


« Reply #7 on: October 05, 2016, 05:48:05 05:48 »

Just to put some color around this -- take DDR3 1333 as an example:

Using this calculator -->  http://referencedesigner.com/tutorials/si/si_06.php

Assume a 6 mil prepreg (H) under top layer, 1 oz copper (T) @ 1.4 mils, and a 5 mil trace width (W) with a dielectric constant of 4.2 (er).
You'll get about 138 ps/inch.

At 667MHz -- but DDR so we're capturing on both edges, so let's figure 1333 -- you get 0.75ns or 750ps per clock edge.  This means that if your traces are <= 750/138 or ~5.4 inches, all of your signals should arrive within a given clock edge, so length matching becomes essentially irrelevant.  On most embedded DDR3 designs, if you're careful with your routing, you should be under 3 inches from CPU to DDR3, so you have plenty of headroom.

Even termination resistors are somewhat optional at this since any reflections tend to get soaked up pretty easily. 


Logged
Gallymimu
Hero Member
*****
Offline Offline

Posts: 579

Thank You
-Given: 101
-Receive: 151


« Reply #8 on: October 06, 2016, 01:35:47 01:35 »


what's DDR???

Hey guys, pretty sure he's talking about Dance Dance Revolution.  
Logged
optikon
V.I.P
Hero Member
*****
Offline Offline

Posts: 604

Thank You
-Given: 460
-Receive: 1604


« Reply #9 on: October 06, 2016, 01:38:43 01:38 »

The design begins with a willing participant and appropriate attire. So yeah, not so easy.


OK promach & unhappy,this might be useful...

http://cache.nxp.com/files/32bit/doc/app_note/AN2582.pdf

Try the game for awhile if you find that your signal integrity is causing read/write errors.

Nothing beats trying and failing for a good education.
« Last Edit: October 06, 2016, 01:45:19 01:45 by optikon » Logged

I can explain this to you. I can't comprehend it for you.
promach
Junior Member
**
Offline Offline

Posts: 43

Thank You
-Given: 14
-Receive: 0


« Reply #10 on: October 07, 2016, 10:31:25 10:31 »

If you want to see how the memory works internally, you can grab a behavioral model from one of the memory vendors (Micron, Samsung, Hynix, etc.)
Sometimes they are sent encrypted, but with a little effort, this can be overcome.

If you're concerned about layout type of things -- DDR layout is not all that it's made out to be.  You have quite a bit of trace length, even at higher clock rates, before length matching will generally matter.  It's a bigger deal with DIMMs than with discrete components.

It is sent encrpyted. What do you mean with little effort ? Are there any open design model that is available ? I mean both verilog model and schematics plus layout
Logged
Pages: [1]
Print
Jump to:  


DISCLAIMER
WE DONT HOST ANY ILLEGAL FILES ON THE SERVER
USE CONTACT US TO REPORT ILLEGAL FILES
ADMINISTRATORS CANNOT BE HELD RESPONSIBLE FOR USERS POSTS AND LINKS

... Copyright 2003-2999 Sonsivri.to ...
Powered by SMF 1.1.18 | SMF © 2006-2009, Simple Machines LLC | HarzeM Dilber MC