Sonsivri
 
*
Welcome, Guest. Please login or register.
Did you miss your activation email?
December 04, 2016, 01:10:52 13:10


Login with username, password and session length


Pages: [1]
Print
Author Topic: [Req] Invite vlsi_emman  (Read 307 times)
0 Members and 1 Guest are viewing this topic.
vlsi_emman
Guest
« on: April 09, 2014, 09:23:41 09:23 »

CountryIndia
NoteHi

I am Emmanuel Vijay from India having more than 3 years of experience in VLSI Industry worked on different Design / Verfication projects.

Have knowledge in HDL Verilog, SystemVerilog, UVM methodology VHDL Embedded C and some conceptual programming in C(not extensively using)

Worked on EDA tools from Mentor graphics Questasim, Cadence IUS, Cadence Virtuoso, Synopsys VCS, Synopsys Prime Time.

Extensively worked on the latest Verification methodology Universal Verification Methodology (UVM) and have good exposure to Soc type verification.

Interested in sharing knowledge and on the same time to gain some knowledge too.

Thanks
Regards,
Emmanuel
Logged
Invitation System
Invitation status : Person isn't invited yet.
Permission : You cannot invite. Because you are guest.
Your credits : You have no invitation credits.

Pages: [1]
Print
Jump to:  


DISCLAIMER
WE DONT HOST ANY ILLEGAL FILES ON THE SERVER
USE CONTACT US TO REPORT ILLEGAL FILES
ADMINISTRATORS CANNOT BE HELD RESPONSIBLE FOR USERS POSTS AND LINKS

... Copyright 2003-2999 Sonsivri.to ...
Powered by SMF 1.1.18 | SMF © 2006-2009, Simple Machines LLC | HarzeM Dilber MC