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Author Topic: [Req] Invite vlsi_emman  (Read 1659 times)
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vlsi_emman
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« on: April 09, 2014, 08:23:41 08:23 »

CountryIndia
NoteHi

I am Emmanuel Vijay from India having more than 3 years of experience in VLSI Industry worked on different Design / Verfication projects.

Have knowledge in HDL Verilog, SystemVerilog, UVM methodology VHDL Embedded C and some conceptual programming in C(not extensively using)

Worked on EDA tools from Mentor graphics Questasim, Cadence IUS, Cadence Virtuoso, Synopsys VCS, Synopsys Prime Time.

Extensively worked on the latest Verification methodology Universal Verification Methodology (UVM) and have good exposure to Soc type verification.

Interested in sharing knowledge and on the same time to gain some knowledge too.

Thanks
Regards,
Emmanuel
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