[Req] Invite RAMESH_K

[RAMESH_K]

Country

india

Note

Skills: Hardware Languages       :  VHDL, VERILOG, system VERILOG (UVM). Software languages       :  C. Hardware design tools                  :  Xilinx (FPGA boards), Mentor Graphics. Layout design tools                        :  Mentor Graphics., Tanner Script languages                             :  PERL. Operating Systems                         :  Windows 98/2000/XP/7/vista, Linux. Certified courses: Under taken VERILOG, SYSTEM VERILOG training at maven silicon BANGLORE Curriculum projects:  On Chip Crosstalk Avoidance Using Low Power Unique Fibonacci Code. •   The project is to develop hardware for circular spatial filter which is useful to suppress the Additive White Gaussian noise (AWGN) in digital images under high noise variance conditions using HDL language VHDL. Xilinx ISE 13.4 tool along with simulator is used. Combination Of Wavelet and Curvelet Based Image Fusion In Medical Applications (DIGITAL IMAGE PROCESSING). •   This project puts forward an image fusion algorithm based on Wavelet Transform and the Second Generation Curvelet Transform. It includes multi resolution analysis ability in Wavelet Transform, also has better direction identification ability for the edge feature of awaiting describing images in the Second Generation Curvelet Transform. This method could better describe the edge direction of images, and analyzes feature of images better. Achievements:   •   Participated in a national level workshop on “VLSI & Image Processing” at Sri Venkateswara college of Engineering & Technology. •   Participated in a national conference at  VIT Chittoor  on “ Recent Advances in Electronics & communication Engineering.

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