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pickit2
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Author Topic: C++ for hardware verification engineers Or I'm Talking Shit Again  (Read 1705 times)
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Aldec_forever
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« on: April 06, 2013, 05:48:02 17:48 »

Lots of methodologies have been emerged for facilitating the verification of Chips. Most of them are based on proprietary languages from EDA vendors. Although UVM is a complete and portable methodology but it's for SystemVerilog. For who wants not to learn new languages other than C++, trusster.com suggests a good method that is all about C++ and teaches you how to verify your DUT using C++ classes, etc.
trusster.com has published a book named Hardware Verification with C++, a practitioner’s handbook that uses the mentioned classes. It's a little different from SCV, but is the only book on the web that teaches C++ for verification. I think it's so valuable and also could help you better understand the SCV.

Simply register and download the source codes. They are needed for accompanying the book.
http://www.trusster.com
Hardware Verification with C++, a practitioner’s handbook
http://depositfiles.com/files/qok0mq7n2


Posted on: March 21, 2013, 10:59:11 22:59 - Automerged

I had the same problem. You have to wait to be approved by Mike.
..................................
All White papers, presentations and source codes from trusster.com:
http://depositfiles.com/files/uyqlruzqq
..................................
You can use it with every verification tool such as Active-HDL, Riviera, etc.


Posted on: March 22, 2013, 06:24:42 06:24 - Automerged

For avoiding creating new thread, I post it here.
Hardware Verification with C++ book is using Verilog PLI. You can use below book for better learning PLI:
......................................
The Verilog PLI Handbook: A User's Guide and Comprehensive Reference on the Verilog Programming Language Interface:
http://bookos.org/s/?q=The+Verilog+PLI+Handbook%3A+A+User%27s+Guide+and+Comprehensive+Reference+on+the+Verilog+Programming+Language+Interface&t=0
......................................
......................................
......................................
Or you can convert your verilog designs and test benches to SystemC by below tool and also use below book for verifying them:
......................................
ADVANCED VERIFICATION TECHNIQUES: A SystemC Based Approach for Successful Tapeout:
http://bookos.org/s/?q=ADVANCED+VERIFICATION+TECHNIQUES%3A+A+SystemC+Based+Approach+for+Successful+Tapeout&t=0

Posted on: March 30, 2013, 08:31:35 08:31 - Automerged

As any SystemC savvy knows, the best book for learning SystemC is "SystemC From the Ground Up". The formal site for that is http://www.scftgu.com/
It has examples for the both editions. They are free but unfortunately I can not download them maybe because of regional problems. Could someone please upload them if possible?
Thanks in advance!

Posted on: April 04, 2013, 02:52:51 02:52 - Automerged

Standard way of Simulating and debugging original SystemC designs by Visual Studio 2008 without modifying them
For simulating and debuging systemc designs you need an IDE like Visual studio. The final release of Visual studio is version 2012 but neither that version nor 2010 one do not support original systemc and you will have lots of errors during compiling because http://www.accellera.org is not based on them. Some major tools have changed the original source and header files for accommodating with the new releases of visual studio but let's forget about them for now.

The best version is 2008. I do not suggest express edition because of not having the enough features. It's better to download VS 2008 Pro Edition. During instalation don't forget that only Visual C++ is needed.

After installing that, it's turn to compile SystemC's original files by Visual C++ and convert them to only a stand-alone SystemC.lib file. It (SystemC.lib) is needed for compiling and simulating your future systemc designs. you can find SystemC's original files from here:
http://www.accellera.org/downloads/standards/systemc

Version 2.3 is a little newer and some tools other than Visual Studio may not work fine with it so download systemc-2.2.0.tgz.

After extracting it to somewhere (consistent place for later need to its source files), just go to ..\msvc71\SystemC folder and open SystemC.vcproj with visual studio 2008 pro and then build it without further manipulation. For other procedures read "INSTALL" file, section 2, "Installation Notes for Windows" (Line 170 and below lines) and follow the steps just one by one.

At the end don't forget to change the "run time library" inside "project/properties/C-C++ tab/" to "Multi-threaded Debug (/MTd)", otherwise you will not be able to compile your systemc designs.

Finally add the examples inside examples folder to the project inside the Visual studio and try to build and simulate them.

Some designs generate VCD files (standard files for saving the e.g. signals' values for viewing them later by a waveform tool). For viewing them just use free tool named gtkwave from http://gtkwave.sourceforge.net/. Just drag your VCD files to the tool.
...............................
Report possible errors. I just followed the above steps and it's working fine. No other tool is needed unless you would want to integrate SystemC with VHDL/Verilog that in this case you'll need to an specialized tool like modelsim. One reason for using Visual Studio IDE is that in it, you do not need to modify your SystemC designs. For example if you try to compile SystemC's examples (not modified form) by modelsim, you'll face with lots of errors because modelsim does not allow the original files to be compiled and you'll need to change them to comply with modelsim compiler's rules that is so awful and wastes a lot of time and needs more experiences but with Visual Studio you don't need even a bit modification.

Posted on: April 04, 2013, 03:18:16 15:18 - Automerged

Among all the modern verification methodologies like AVM (from Mentor), OVM(from Mentor and a little newer than AVM), VMM(Synopsys), UVM(Cadence and mentor- The final one but unfortunately is most based on SystemVerilog), only AVM has useful verification libraries for SystemC and C++ users. Others have been implemented in SystemVerilog (that I hate it much).

Below post has "class libraries + cookbook +examples" for accompanying AVM methodology. By learning that you can also learn other methodologies easily because of consisting almost the same framework.

Don't forget that learning new nowadays designs and verification paradigms needs strict knowledge of C++ classes. Without learning them, you will never be able to learn anything (Modeling and Verification).

So choose one bible form http://www.sonsivri.to/forum/index.php?topic=51730.0 and try to raise your class knowledge and nothing else. Designing and verification in TLM and RTL levels with SystemC, SCV and SystemVerilog are strictly depending on how much you know about classes.
I suggest Beginning Visual C++ 2012:
http://www.sonsivri.to/forum/index.php?topic=47887.0
http://www.sonsivri.to/forum/index.php?topic=47807.0

For simulating them you need modelsim or questasim.
« Last Edit: April 07, 2013, 02:28:24 02:28 by Aldec_forever » Logged

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« Reply #1 on: April 08, 2013, 02:04:38 14:04 »

SystemC Verification is based on Test Builder (acquired by Cadence then donated to SystemC.org (now accellera.org you know)). Test builder was the first verification tool based on C++ and because the verilog was dominant those day (year 2000), Test builder was trying to communicate with it.

After releasing the first version of SystemC and lots of hopes and succeeds about it and also allowing to model the most abstraction levels including TLM, RTL ,etc in it (SystemC), SCV by deriving from test builder classes emerged to cover the SystemC designs. Because with SystemC, Verilog is remained to cover only the gate level simulations although SystemVerilog has been advanced to complete the Verilog. I read somewhere that about 90% of nowadays designs are accomplished by C++/SystemC and SystemVerilog is only used for verification. This shows the importance of C++/SystemC.

Below is the manual of test builder (passed away). You can compare it with SCV libraries and components. Inquisitive user would find that test builder is constituting most parts of SCV.

testbuilderref.pdf
http://www.ee.virginia.edu/~mrs8n/soc/SynthesisTutorials/testbuilderref.pdf
OpenSourceTestBuilderCPlusPlusClassLibrary.pdf
http://co-consulting.net/OpenSourceTestBuilderCPlusPlusClassLibrary.pdf
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« Reply #2 on: May 18, 2013, 12:34:29 12:34 »

Hi!
As every SystemC user know, modeling in TLM2 is the most complicated job for the developers and because of misunderstanding the TLM concept, it seems that TLM2 would be undiscoverable.

I believe that most aspects of modeling and verification tasks are for software designers not hardware ones. TLM2 is one of those aspects and the reason why hardware designers with verilog background have always trouble with that is this.

Modeling with C++ is 1000000.... order more complicated than verilog and most hardware designers are not savvies of using classes inside C++. Most of the users of even micro controllers are C ones not C++ ones and are not familiar with classes.

C++ for nowadays SOC designers is a need and without learning it you will never ever be a good designer specially when you're dealing with communication aspects of design.

Below is the best resource for TLM2 lovers. It's compliant with the latest version of TLM2. It needs moderate knowledge of SystemC. I suggest it as a Bible
...................................
http://www.starc.jp/tlmg/index-e.html

Posted on: May 11, 2013, 06:32:28 06:32 - Automerged

Has anyone tried to use TLM2 (accellera's standard) for architecture design in LT or even AT levels for real applications including processors and hardware accelerators and also peripherals models ? I'll be so glad to hear the personal experiences other than the literature because of omitting most details in them.
Sincerely yours!
Aldec_forever
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« Reply #3 on: May 22, 2013, 12:56:24 00:56 »

Hi!
As every SystemC user know, modeling in TLM2 is the most complicated job for the developers and because of misunderstanding the TLM concept, it seems that TLM2 would be undiscoverable.

I believe that most aspects of modeling and verification tasks are for software designers not hardware ones. TLM2 is one of those aspects and the reason why hardware designers with verilog background have always trouble with that is this.

Modeling with C++ is 1000000.... order more complicated than verilog and most hardware designers are not savvies of using classes inside C++. Most of the users of even micro controllers are C ones not C++ ones and are not familiar with classes.

C++ for nowadays SOC designers is a need and without learning it you will never ever be a good designer specially when you're dealing with communication aspects of design.

Below is the best resource for TLM2 lovers. It's compliant with the latest version of TLM2. It needs moderate knowledge of SystemC. I suggest it as a Bible
...................................
http://www.starc.jp/tlmg/index-e.html
This is the most confounding and complicated doc I have ever read. Does any tool exist for putting the mentioned concepts in the guide into practice?
Thanks!
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« Reply #4 on: May 29, 2013, 08:23:18 20:23 »

All of major EDA vendors have ESL tools that have been specialized for this. For example Mentor Vista is one of them.

Posted on: May 22, 2013, 12:50:28 12:50 - Automerged

To SystemC and TLM2 lovers:
http://www.ocpip.org/
.............................
OCP-IP is dedicated to proliferating a common standard for intellectual property (IP) core interfaces, or sockets, that facilitate "plug and play" System-on-Chip (SoC) design. Making complex SoC design more efficient for the widest audience, the industry strongly supports the Open Core Protocol as the universal complete socket standard, regardless of on chip architecture or which processor cores are featured.
.
.
.
.
.
Below pic shows TLM based OSCI and OCP-IP models interoperability. By reading STARC TLM GUIDE (http://www.sonsivri.to/forum/index.php?topic=51588.msg150714#msg150714), you'll fully understand the below pic's operating mechanism.

Posted on: May 26, 2013, 07:24:43 19:24 - Automerged

To SystemC and TLM2 lovers:
http://www.greensocs.com/
.............................
GreenSocs® offers a complete range of high productivity solutions for SystemC Model Based Design of Embedded Systems.

Posted on: May 27, 2013, 05:12:41 05:12 - Automerged

Good docs for learning TLM (the most successful methodology for BUS and NOC based designs) based SOC modeling and implementation:
http://www.ocpip.org/white_papers.php

Specially OCP TLM for Architectural Modeling (Only 30 pages):
http://www.ocpip.org/uploads/documents/OCP_TLM_for_Architectural_Modeling.pdf
...................................
TLM allows to realize all of below network topologies among heterogeneous blocks. TLM is majorly for the separation of communication and computation in all blocks that allows models of blocks to be plugged into the overall system without worrying about the communication protocols.

Posted on: May 28, 2013, 06:29:04 18:29 - Automerged

TLM based models exchange (the only official site):
http://www.tlmcentral.com/models/

There are currently 993 models to look at. The amount of TLM-2 bus based models is 543. This shows the importance of TLM-2.
Models have been categorized as:
Abstraction Level
    Other
    Loosely-Timed
    Approximately-Timed
    Cycle-Accurate
    Instruction-Accurate
    Fast-Timed
IP Type
    Other
    Processor
    Interconnect
    Peripheral
Bus Interface
    Other
    TLM-2.0
    AMBA-PV
    AHB
    AX13
    AX14
    OCP
Market Category
    Wireless
    Automotive
    Consumer
    Defense
    Other

Posted on: May 29, 2013, 02:18:33 14:18 - Automerged

Could someone please register to http://www.ocpip.org with a company or an university account?
http://www.ocpip.org/tlm_kit.php
Its materials are so valuable. I need its toolkit and private models. I guess they would be useful for the others too.
Thanks so much!
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« Reply #5 on: May 30, 2013, 06:22:37 18:22 »

All of major EDA vendors have ESL tools that have been specialized for this. For example Mentor Vista is one of them.
Thanks so much for your suggestion. I investigated the other tools' datasheets too and found Vista is the best tool for TLM-2 based designs. Anyway I have downloaded Vista 3.5 (Linux-32bit) from EETOP and applied http://www.sonsivri.to/forum/index.php?topic=50957.0 you have posted with appropriate mentor key but unfortunately it did not patched anything:

./sfk rep -pat -yes -bin /5589E557565381ECD00000008B5508/31C0C357565381ECD00000008B5508/ -dir .

I think new key is needed. Has anyone succeeded to find the new key. I need this tool.

Thanks in advance!
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« Reply #6 on: May 30, 2013, 08:08:50 20:08 »

I had the same problem and copied http://depositfiles.com/files/58rckm191 files and problem solved for now. New key is needed for future releases.
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« Reply #7 on: May 30, 2013, 09:21:17 21:21 »

Thanks yes it was solved and works fine. Tongue I also compiled my first project. Your posted STARC TLM GUIDE is unique. It's the best tutorial for TLM-2 in the web.
« Last Edit: May 30, 2013, 09:25:39 21:25 by ESL_HLS » Logged

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« Reply #8 on: September 15, 2013, 12:36:07 00:36 »

SystemC and TLM-2 technologies both have lots of files and classes. The first step for understanding them is having full visibility to their internal structure. Doxygen is an excellent tool for documenting source codes including C++. Then you can explore classes, view their members and variables and also dependability among them graphically and eventually life gets easy. TLM-2 (only 2009 version) has done it before but SystemC itself needs it.

http://www.sonsivri.to/forum/index.php?topic=52561.0
Creating documentation with Doxygen is like playing with a toy.


Posted on: June 02, 2013, 07:39:05 19:39 - Automerged

It is a tedious task to discover the intent the SystemC and TLM2 authors by just looking at the source codes and if you don't do that you will never be able to write cores.

I have tried to provide documentations about the class dependency and more by diagrams. It facilitates and reduces the design time even for savvies. It's the first time in the web that such documentation is being published. Hope it'd be useful.

If the shortcut link inside the root folder did not work, just open "index.html" inside "SystemC & TLM2" folder.
http://depositfiles.com/files/6cfakgnq5

BTW, SCV 2.0 is available for public review (I'll provide documentation for that too soon):
"The SystemC Verification Working Group has begun a public review of the SystemC Verification Library 2.0, an update to SCV 1.0p2."
http://www.accellera.org/activities/committees/systemc-verification/



Posted on: July 06, 2013, 09:18:18 21:18 - Automerged

Hi everybody!
If anyone wants to compile and simulate SystemC applications inside Aldec Riviera (instead of using visual studio that lacks appropriate tools for viewing and debugging), please informs me. I will explain it in a simple way.
Good luck!

-------------------------------------
-------------------------------------
-------------------------------------

For being able to compile and simulate SystemC applications inside Visual Studio 2012 (HLS tools still work with version 2008), read below page:
http://forums.accellera.org/topic/126-systemc-in-visual-studio-2012/
For defining environment variable named "SYSTEMC", you must do like below. If you point to other folder, compilation process fails.

SYSTEMC  --->>>  c:\systemc-2.3.0\msvc80

Posted on: September 14, 2013, 08:33:52 20:33 - Automerged

Some good tutorials:
http://www.embecosm.com/resources/appnotes/
« Last Edit: September 15, 2013, 11:22:30 11:22 by Aldec_forever » Logged

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« Reply #9 on: September 20, 2017, 01:38:35 01:38 »

This is the same Member talking to himself...
And wonders why I mute his accounts in the Forum...
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