Unfortunately I don't have time to extract the exact schematic from USBee SX but it is almost the same with the attached schematic...
Unfortunately the difference between the schematic you posted and the SX/ZX (which I do not own) are various:
- the bidirectionality of the I/O pod port (no jumper to be set)
- support of the CLOCK and TRG lines.
- the CLOCK line seems to be bidirectional (it can accept an external clock signal for synchronous capture)
I do not know if the ElraSoft one has the same capabilities as the SX/ZX (except for the 16bit I/O)
Maybe some of the Sonsivri members have also the schematics of the SX/ZX: I will be grateful if they can post it.
(i tried to access the russian forum, but I wasn't able to register, so downloads are disabled)
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Edited some hours later....
OK, some of my assumptions were wrong: I installed Proteus and opened the schematics of the AX device and it seems that the developers of USBee (SX/ZX) didn't put ANY buffering/protection on the I/O ports of the CY7C68013A!!!
Except for the 100 Ohm resistors/diodes combination, there are NO buffers (SN74LVC8T245).
I think this is really poor design and now I understand why they are rather shy about the input/output voltage maximum/minimum ratings on their web site!
If you will use the USBee with lower voltage devices (1.8/2.5V) you can have problems...
The "CLOCK" signal is always in Output mode.
Instead the "TRG" line is used for synchronous capture and is DIRECTLY connected to the Cypress chip...
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Do you know how do the other products (Logic/ElraSoft/...) behave on such matters?