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Author Topic: Synchronous Counter(4 Bit using T Flip Flop, onboard Clock reduced to 1Hz)  (Read 6705 times)
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mtech84
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« on: November 09, 2009, 07:51:11 07:51 »

Procedure:

1.   Create a new project in Quartus II on your personal storage device.
2.   Create a new VHDL file for the 4-bit T-Flip-Flop synchronous counter shown below.
3.   Assign Enable to SW[0], assign CLK to KEY[0], and assign SW[1] to select between the manual clock, KEY[0], and the onboard 50 MHz clock on the DE2 board.
4.   Implement the code, attached with this post(DE2 clk_div.vhd) , to reduce the 50 MHz clock to 1 Hz.

5.   Assign the Q outputs of each T-flip flop to display LEDR[3-0].
6.   Perform a functional simulation to verify the operation of the counter.
7.   Download the program onto the DE2 board.
8.   Verify the operation of the counter manually with KEY[0] and the onboard clock.

can somebody help me on 3 and 4 point...plz thnks......

« Last Edit: November 14, 2009, 11:29:35 23:29 by mtech84 » Logged
fpgaguy
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« Reply #1 on: November 10, 2009, 04:08:02 04:08 »

for #3, this is not done typically in VHDL file -
You'll have to open the pin mapper function in quartus and set those I/O bits to the correct pins as your board is wired.

but the other problem is you didn't do #2 yet
Once you do that, you'll have an enable and clear, clock and q/*q outputs from a new entity that matches the schematic 123.jpg


you'll need to add an input to your entity for these other pins omitted

port (
.... your existing stuff....
  enable : input std_logic;
  clear : input std_logic;
... your other stuff....
)

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mtech84
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« Reply #2 on: November 10, 2009, 05:41:41 05:41 »

thnks man i am trying to get the basics right and once that is done i will be done with this and i post the correct solution.


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mtech84
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« Reply #3 on: November 14, 2009, 11:27:47 23:27 »

complete vhdl code below, just import the pins assignment file , go to tools-->programmer--> start, in altera to program the de2 board.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY counter IS
PORT ( CLOCK_50 : IN STD_LOGIC;
SW: IN STD_LOGIC_VECTOR(1 downto 0);
KEY: IN STD_LOGIC_VECTOR(0 downto 0);
LEDG : OUT STD_LOGIC_VECTOR(8 DOWNTO 5);
HEX0 : OUT STD_LOGIC_VECTOR(0 TO 6));
END counter;


ARCHITECTURE Behavior OF counter IS

COMPONENT hex7seg
      PORT (   hex      : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
               display  : OUT STD_LOGIC_VECTOR(0 TO 6));
   END COMPONENT;


SIGNAL hex : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL slow_count : STD_LOGIC_VECTOR(24 DOWNTO 0);
SIGNAL temp : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal tog : std_logic;
signal enable : std_logic;
SIGNAL tempy : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN

PROCESS (SW(0))
begin
      if (SW(0) ='1') then
      enable <= '1';
      else
      enable <= '0';
      end if ;
   end process;

PROCESS (CLOCK_50)
begin
   IF (CLOCK_50'EVENT AND CLOCK_50 = '1') then
      if (SW(1) ='1' AND SW(0) ='1') then
      tog <= '1';
      else
      tog <= '0';
      end if ;
   end if;
end process;

PROCESS (SW(0),CLOCK_50)
BEGIN
IF (CLOCK_50'EVENT AND CLOCK_50 = '1' AND SW(0) = '1') THEN
slow_count <= slow_count + '1';
END IF;
END PROCESS;

process (KEY(0))
      begin
      if (KEY(0)'event and KEY(0) = '0') then
         if (enable <= '1' AND tog = '1') then
            if tempy < 15 then
            tempy <= tempy + '1';
            else
            tempy <= "0000";
            end if;
         elsif (enable <= '1' AND tog ='0') then
          tempy <="0000";
          elsif ((enable <= '0' AND tog ='0') OR (enable <= '0' AND tog ='1')) then
         tempy <= tempy;
          end if;
      end if;
   

END PROCESS;
PROCESS (CLOCK_50)
BEGIN

   IF (CLOCK_50'EVENT AND CLOCK_50 = '1') THEN
      
      IF (slow_count = 0) THEN
         IF (temp = "1111") THEN
         temp <= "0000";
         ELSE
         temp <= temp + '1';
         END IF;
      END IF;
      if (enable <= '1' AND tog = '1') then
      temp <= "0000";
      elsif ((enable <= '0' AND tog ='0') OR (enable <= '0' AND tog ='1')) then
      temp <= temp;
      end if;
   END IF;

END PROCESS;
LEDG <= temp OR tempy;
hex <= temp OR tempy;
-- drive the display through a 7-seg decoder
   digit_0: hex7seg PORT MAP (hex, HEX0);
END Behavior;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY hex7seg IS
   PORT (   hex      : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
            display  : OUT STD_LOGIC_VECTOR(0 TO 6));
END hex7seg;
ARCHITECTURE Behavior OF hex7seg IS
BEGIN
   PROCESS (hex)
   BEGIN
      CASE hex IS
         WHEN "0000" => display <= "0000001";
         WHEN "0001" => display <= "1001111";
         WHEN "0010" => display <= "0010010";
         WHEN "0011" => display <= "0000110";
         WHEN "0100" => display <= "1001100";
         WHEN "0101" => display <= "0100100";
         WHEN "0110" => display <= "1100000";
         WHEN "0111" => display <= "0001111";
         WHEN "1000" => display <= "0000000";
         WHEN "1001" => display <= "0001100";
         WHEN "1010" => display <= "0001000";
         WHEN "1011" => display <= "1100000";
         WHEN "1100" => display <= "0110001";
         WHEN "1101" => display <= "1000010";
         WHEN "1110" => display <= "0110000";
         WHEN OTHERS => display <= "0111000";
      END CASE;
   END PROCESS;
END Behavior;
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