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Author Topic: [REQ] Viterbi Decoding  (Read 1323 times)
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RedBull
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« on: October 17, 2009, 07:17:39 07:17 »

Does anyone have materials related to implementation of Viterbi algorithm using VHDL on FPGA? Any information would be very helpful.
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DarkClover
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« Reply #1 on: November 02, 2009, 06:05:43 18:05 »

There is a lot of Information about the Viterbi algorithm and FPGA on the internet:

First is Wikipedia but I'm sure you have read this. (http://en.wikipedia.org/wiki/Viterbi_algorithm)
Have a look at the attachments there are some projects using the Viterbi algorithm.
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janakfun
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« Reply #2 on: November 18, 2009, 11:36:33 11:36 »

If you are looking for VHDL implementation of the same ,let me please know the K  and r values you wish to have for the algorithm .
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Janak
RedBull
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« Reply #3 on: November 20, 2009, 02:00:39 14:00 »

If you are looking for VHDL implementation of the same ,let me please know the K  and r values you wish to have for the algorithm .

I'm looking to implement K=3 and r=1/2 decoder first. Then i'll do it for higher K value.
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janakfun
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« Reply #4 on: December 16, 2009, 11:34:54 11:34 »

Hi
sorry for the late reply, i was a bit busy.
Anyway , please find in this link ,
 http://www.expertcore.org/viewtopic.php?f=8&t=866

this could may be useful to you. please try some code converter tools as the code is in C++ .
or
 Try this code from open cores .

  http://www.opencores.org/project,vhcg

 (this is in VHDL, for k= 7 , r= 1/2 )

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Janak
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