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Author Topic: Tl494/SG3525 Duty Cycle Issue???  (Read 7516 times)
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thetrueman
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« on: January 27, 2009, 11:16:51 11:16 »

Hi all,

I wonder that there is no detail in the datasheet of SG3525 that how we can use sync pin of this IC. How it effects the output? what would be the waveforms? Anybody have expericence with this? Please guide... Thanks.
« Last Edit: February 16, 2009, 10:57:12 10:57 by thetrueman » Logged
kayvee
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« Reply #1 on: January 27, 2009, 11:34:09 11:34 »

Did you read the accompanying app note, there is some reference to it and how to use it in there.

http://www.st.com/stonline/products/literature/an/1689.htm
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HackerNo.1
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« Reply #2 on: January 27, 2009, 05:57:21 17:57 »

For thetrueman,
All sorts of practical data are not always available in Datasheet.
Sync pin (pin no.3) and osc out pin (pin no.4) are used when more than one sg3525 are used simultaneously in Master- Slave configuration. It is a bit difficult to apply and moreover in most cases one sg3525 is used at a time, which is suffice for most of the circuits, either Low Freq or High Freq application. So, leave those 2 pins unattended and use other pins and it will not effect your circuit anyway. Have a good day.
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tAhm1D
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« Reply #3 on: January 28, 2009, 06:40:42 06:40 »

Hi,
HackerNo.1 is correct. I have experience in it. This syn pin is used when one sg3525 is used as Master and other sg3525 used as slave/slaves. But one problem is there. Time constant of Master and slaves can not be kept same as Time constant of slave ic should be >10-30% than the Master ic. So, synchronization within all Master and Slave ics is a bit difficult. One can do it but it requires so much test and trial that it is wise to use separate ics with individual osc instead of sync with Master and Slave. Moreover, with one ic, very high power inverter/power supply can be made, keeping those 2 pins unattended.
« Last Edit: January 28, 2009, 06:45:49 06:45 by tAhm1D » Logged
thetrueman
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« Reply #4 on: February 16, 2009, 11:10:42 11:10 »

Hi All,

Can we limit Duty Cycle to minimum 10% to avoid going below this point in any SMPS IC? i.e. if output is too high and feedback reduces the duty cycle to low the output then at one stage the duty cycle would be 0% but I need it to be 10% even the output is high. Is there ay way? Please suggest... Thanks.

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Walkura
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« Reply #5 on: February 21, 2009, 01:03:49 13:03 »

Hi All,

Can we limit Duty Cycle to minimum 10% to avoid going below this point in any SMPS IC? i.e. if output is too high and feedback reduces the duty cycle to low the output then at one stage the duty cycle would be 0% but I need it to be 10% even the output is high. Is there ay way? Please suggest... Thanks.


Good afternoon Thetrueman .
You calculate the minimum and maximum dutycycle during the design process .
How much duty change you allow or want to happen is something you calculate and adjust your component value's for .
From what i recall feedback voltage is something between 0.9 to 3.9 Volt on the comperator input .
By limiting that to lets say lowest from the feedback is ~1.3 Volt then you have duty from 10% up .
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tAhm1D
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« Reply #6 on: February 23, 2009, 04:47:23 16:47 »

Hi thetrueman,
Walkura's answer is correct in respect to your question and you can find it if you dig the datasheet of sg3525. But one advice to you, don't disturb the internal architecture of the above mentioned pwm- ed  ics. Try to fulfill your requirement through additional passive components and designing intelligent feedback system.
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