Can we limit Duty Cycle to minimum 10% to avoid going below this point in any SMPS IC? i.e. if output is too high and feedback reduces the duty cycle to low the output then at one stage the duty cycle would be 0% but I need it to be 10% even the output is high. Is there ay way? Please suggest... Thanks.
Good afternoon Thetrueman .
You calculate the minimum and maximum dutycycle during the design process .
How much duty change you allow or want to happen is something you calculate and adjust your component value's for .
From what i recall feedback voltage is something between 0.9 to 3.9 Volt on the comperator input .
By limiting that to lets say lowest from the feedback is ~1.3 Volt then you have duty from 10% up .