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Author Topic: at89c52 Code Banking  (Read 3595 times)
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« on: October 12, 2008, 06:11:51 06:11 »

Hi,

Please can anyone help me?
I'm using at89c52. Can you guide me how to do the configuration keil code banking?

I have do some testing. I create x1 common x3 bank's. After i compiled, it just generate the 3 bank hex file. May i know how to generate the common.c hex file? Is it necessary to have common.hex to burn into MCU? The x3 bank.hex will be in to EPROM.

Please can you check for me is it the circuit correct not?

Thank you very much.....
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pablo2048
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« Reply #1 on: October 14, 2008, 11:00:14 11:00 »

Hi, maybe this help http://www.keil.com/support/docs/2084.htm
(if You are using Keil > 6.x)
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« Reply #2 on: October 14, 2008, 04:08:37 16:08 »

Hi,

Thank for your reply. I still not understand how to configure the setting. Please can you guide me?

Thank you.
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« Reply #3 on: October 15, 2008, 07:22:30 19:22 »

Hi,

Thank for your reply. I still not understand how to configure the setting. Please can you guide me?

Thank you.
Ok, first in Your schematic (seen from .pdf) pin 1 U5:A MUST be grounded (otherwise bank decoder doesn't work), next IMHO you can't use P1 and P3 at the same time - look at the L51_BANK.A51 line 44-47 and finally follow this guide for 'burning' ROM's
http://www.keil.com/support/docs/158.htm
Notice that common area is in ALL ROM hex files!!!
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« Reply #4 on: October 15, 2008, 07:58:51 19:58 »

Hi,

Thank for your advice. I already change redesign the circuit again. I will use MCU A15 to control the U5:A. Please have a look..
Ya, the L51_BANK.A51 line 44-47 show define the P1 and start bit. But at the L51_BANK.A51 line 98-113 have use P3.3. May i know how they control the Bank Switching? Actually i'm not familiar with the Assembly language.

If all the common area is in ROM. If i create x1 common x3 bank's, so i must have 4 ROM's rite? If yes, how about the AT89C52 hex file?

Now i plan use SRAM to store the CODE. I don't have a burner for ROM and erase tool for that. So, i need to do a bootloader for download the CODE to SRAM. But i think the concept for the Bank Switching will be the same, am i rite?

Please advice...

Thank you.
« Last Edit: October 15, 2008, 08:03:45 20:03 by Help » Logged
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« Reply #5 on: October 16, 2008, 06:44:06 18:44 »

Hi,

Thank for your advice. I already change redesign the circuit again. I will use MCU A15 to control the U5:A. Please have a look..
Ya, the L51_BANK.A51 line 44-47 show define the P1 and start bit. But at the L51_BANK.A51 line 98-113 have use P3.3. May i know how they control the Bank Switching? Actually i'm not familiar with the Assembly language.

If all the common area is in ROM. If i create x1 common x3 bank's, so i must have 4 ROM's rite? If yes, how about the AT89C52 hex file?

Now i plan use SRAM to store the CODE. I don't have a burner for ROM and erase tool for that. So, i need to do a bootloader for download the CODE to SRAM. But i think the concept for the Bank Switching will be the same, am i rite?

Please advice...

Thank you.
forget about lines 98-113 - you have selected banking mode 0 (line 14) and lines 98-113 are for banking mode 4. These macros are never used!! According to your new schematic IMHO change:
?B_FIRSTBIT EQU 0
Where you plan to store code before loading into SRAMs? Yes - bank switching scheme is the same but don't forget to set DPTR and P1 properly while downloading XDATA.
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« Reply #6 on: October 16, 2008, 07:24:09 19:24 »

Hi,

May i know..
Q1: What's the different mode 0 and mode 4 at line 14? On my situation, if i plan to have x3 SRAM for CODE and x1 DATA.
Q2: What mode should i set? and how can i control the switching according to my schematic? (my schematic design, OK?)
Q3: How to generate the common hex file? What hex file AT89C52 need to be burn?
 
The data in SRAM will be lose after the power is off. So i have a idea which is add another external buffer EEPROM or MMC/SD card when power is ON the external buffer CODE data will copy it to SRAM. With this method i can have a huge memory spacing and no worry about the CODE/DATA limitation. May be have to do the bootloader when power is on. Initial state will using UART to update the CODE in RAM first.
Is it possible to do that? Do you have any idea?

Please advice..
Thank you...
« Last Edit: October 16, 2008, 07:27:11 19:27 by Help » Logged
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« Reply #7 on: October 16, 2008, 08:16:05 20:16 »

Hi,

May i know..
Q1: What's the different mode 0 and mode 4 at line 14? On my situation, if i plan to have x3 SRAM for CODE and x1 DATA.
Q2: What mode should i set? and how can i control the switching according to my schematic? (my schematic design, OK?)
Q3: How to generate the common hex file? What hex file AT89C52 need to be burn?
 
The data in SRAM will be lose after the power is off. So i have a idea which is add another external buffer EEPROM or MMC/SD card when power is ON the external buffer CODE data will copy it to SRAM. With this method i can have a huge memory spacing and no worry about the CODE/DATA limitation. May be have to do the bootloader when power is on. Initial state will using UART to update the CODE in RAM first.
Is it possible to do that? Do you have any idea?

Please advice..
Thank you...
Hi,
A1: Banking modes differ in mechanism for HW switching banks - for more information read http://www.keil.com/support/docs/1059.htm
A2: According to your schematic use banking mode 0 - bank is selected by some pins of port P1-3, the only change you need is modification of ?B_FIRSTBIT as i suggested.
A3: Do you read the link, which i posted? Common area is in ANY generated hex file (again - the link is http://www.keil.com/support/docs/158.htm )
And finally it is possible do it your way, but its not so easy - for example you can't forget to move interrupt vectors to RAM area and in your banking program loaded from external buffer you must set origin above internal CODE memory in 89C52.
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« Reply #8 on: October 17, 2008, 07:18:34 07:18 »

Hi,

I think i already understand the Q1, and Q2.
About the Q3, yes, before i post this topic here. I also read few time already. But i still not understand it Sad Please can you create a simple sample for me to test? May be have a practical then i will know more detail..
Do you mean have to use 89c52 write the CODE in SRAM will not easy? mean when power is up have to do the copy from external buffer (EEPROM/MMC/SD) data to SRAM then after finished copy have to run it in origin code banking will be not easy?
What can i do now? I already do the ASCII to Intel-hex conversion part on the coding.

Please advice..
Thank you.
« Last Edit: October 17, 2008, 07:25:39 07:25 by Help » Logged
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« Reply #9 on: October 20, 2008, 04:22:41 16:22 »

Hi,

I think i already understand the Q1, and Q2.
About the Q3, yes, before i post this topic here. I also read few time already. But i still not understand it Sad Please can you create a simple sample for me to test? May be have a practical then i will know more detail..
Do you mean have to use 89c52 write the CODE in SRAM will not easy? mean when power is up have to do the copy from external buffer (EEPROM/MMC/SD) data to SRAM then after finished copy have to run it in origin code banking will be not easy?
What can i do now? I already do the ASCII to Intel-hex conversion part on the coding.

Please advice..
Thank you.
Ok, there is no simple sample - the simpliest one is your project - just look into generated HEX files. I don't understand what is so unclear in following text (pasted from Keil...):
"Assuming that the bank area is from 0x8000 to 0xFFFF (which implies that the common area is from 0x0000 to 0x7FFF), each HEX file will have the common area from 0x0000 to 0x7FFF. Yes, the common area is stored in EACH HEX FILE. Each HEX file will also have the code bank code from 0x8000 to 0xFFFF."
and
"If you use separate EPROMs for the common and bank areas, first pick one of the HEX files (it doesn't matter which one) and program the COMMON EPROM using the data from 0x0000 to the end of the common area."
By the way in 8051 CPU has to be burned bootstrap, no common bank. Please draw memory map of your design for yourself and i hope it will be clear...
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« Reply #10 on: October 21, 2008, 06:33:46 06:33 »

Hi pablo2048,

Thank you very much for giving very clear explanation.
Keil will generate .bin and .hex file. May i know, what format EPROM will accept? .bin or hex file? Temporary using EPROM to do simulation.

Another question is from my simulation the program alway switch to Bank2 and call the func2 although we never call from other Bank, what make cause it alway call the func2 when alway calling the func0 or func1? and the func0 and func1 message alway can't display out. Is there any wrong setting on compiler? Please can you check for me?

Now i pick any one of the HEX file to run in 89c52. May i know if the HEX file store the common area data and the code bank code will cause the HEX file size increase? If yes, 89c52 internal rom data will easly to get overflow, am i rite?

Can we hard code the bootstarp in 89c52. For initial state, may be we can put a external jumper. This jumper function is either for Download Hex file or Normal mode. May be the memory mapping will be more flexible. When 1st time download the Hex data to external EEPROM/SD will record down all the CODE BANK code size. So, when power is ON and jumper is on Normal mode then the 89c52 will send what ever data is within the code size have to the SRAM and will continue to send to next SRAM if there is the data in EEPROM. Is it ok?

Thank you.
« Last Edit: October 21, 2008, 06:38:39 06:38 by Help » Logged
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« Reply #11 on: October 24, 2008, 09:07:11 09:07 »

Hi,
as i said, i don't have Proteus so i can't check your simulation. You may check this:
1. correct offchip data memory size - you have specified start RAM 0x4100 and size 0x7f00. That is wrong.
2. turn on generating assembly code in C listing and check generated assembly code
3. uncheck Run to main in Debug and do stepping in disassembly window

In EPROM is of course stored binary image.
As i see you are beginner with microcontroller so i advice to start with some simple project and not with this one (write bootloader for banking isn't simple task for beginner). 
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« Reply #12 on: October 25, 2008, 10:43:59 10:43 »

Hi,

Q1: If i set the RAM 0x4100 and size 0x0100. Is it ok? I think the sample code din't use the external data. I think size 0x0100 should be fine.
Q2: I'm not so familiar with assembly code. I have check and see the Disassembly window when stepping debug. It work fine. All the message will display out on Serial window. Is it something wrong with the circuit?
Q3: And i realize the P3.7 /RD pin look like no function!!

I have use at89c52 2 years already. Normaly the 8k CODE is enough for me to do some simple hobby application. So, i'm not care about the CODE size and the addressing.
May be it is very difficult for me but i would like to try my best. Just hope got people can guide me. I have trying this thing almost few mounths already.

I hope you don't mind i'm a beginner and teach me a difficult task.

Thank you very much..
« Last Edit: October 25, 2008, 10:51:28 10:51 by Help » Logged
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« Reply #13 on: November 06, 2008, 03:31:17 15:31 »

Hi,

Q1: If i set the RAM 0x4100 and size 0x0100. Is it ok? I think the sample code din't use the external data. I think size 0x0100 should be fine.
Q2: I'm not so familiar with assembly code. I have check and see the Disassembly window when stepping debug. It work fine. All the message will display out on Serial window. Is it something wrong with the circuit?
Q3: And i realize the P3.7 /RD pin look like no function!!

I have use at89c52 2 years already. Normaly the 8k CODE is enough for me to do some simple hobby application. So, i'm not care about the CODE size and the addressing.
May be it is very difficult for me but i would like to try my best. Just hope got people can guide me. I have trying this thing almost few mounths already.

I hope you don't mind i'm a beginner and teach me a difficult task.

Thank you very much..
Ok,i'm back for a while...
A1: Yes, it's ok - Your code does'nt use XRAM YET :-)
A2&3: I'm not familiar with Proteus - just try to tie EA to GND directly (no SW1) and run all Your code from external EEPROM. Or write some simple non-banked code to test simulator ;-) ... wait a moment - RD signal works ONLY with XRAM, external code is fetched by PSEN AFAIK... You may try following simple code to test XRAM:
xdata unsigned char c;
void main(void)
{
  c = 0;
  for (;;Wink
  {
    c++;
  }
}
Both RD and WR signal must indicate access to xdata...
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« Reply #14 on: November 16, 2008, 05:32:44 17:32 »

Hi ablo2048 fren,

I'm back. Smiley
Sorry for disappear so long. Ya, I have finished my downloader. Now i able to run my code on sram already. After the code is downloaded then have to set the EA to GND. Currently i have two 32kB SRAM and one 128kB SRAM. How can i do the bank switching?

May i know what's the next step i should do?

Thank you.
« Last Edit: November 16, 2008, 05:36:33 17:36 by Help » Logged
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« Reply #15 on: November 18, 2008, 04:07:34 16:07 »

Hi Help,
nice to hear You again. I prefer another way to do it - i made small assembler file named vector.a51:
Code:
Offset set 2000h
CSEG AT 0003h
ljmp $+Offset
CSEG AT 000Bh
ljmp $+Offset
CSEG AT 0013h
ljmp $+Offset
CSEG AT 001Bh
ljmp $+Offset
CSEG AT 0023h
ljmp $+Offset
CSEG AT 002Bh
ljmp $+Offset
CSEG AT 0033h
ljmp $+Offset
CSEG AT 003Bh
ljmp $+Offset
CSEG AT 0043h
ljmp $+Offset
CSEG AT 004Bh
ljmp $+Offset
CSEG AT 0053h
ljmp $+Offset
CSEG AT 005Bh
ljmp $+Offset
CSEG AT 0063h
ljmp $+Offset
CSEG AT 006Bh
ljmp $+Offset
CSEG AT 0073h
ljmp $+Offset
CSEG AT 007Bh
ljmp $+Offset
CSEG AT 0083h
ljmp $+Offset
CSEG AT 008Bh
ljmp $+Offset
CSEG AT 0093h
ljmp $+Offset
CSEG AT 009Bh
ljmp $+Offset
CSEG AT 00A3h
ljmp $+Offset
CSEG AT 00ABh ; only for C8051F020, NOT for C8051F120
ljmp $+Offset
end
Then include this file in Your bootloader.
When You are setting and building main application (not bootloader) set in Keil uVision->Options->C51 "Interrupt vectors at address: 0x2000"
And in Target->Off-chip Code memory: 0x2000 0xD000
In Your bootloader You have to jump to location 0x2000 when loading is done - main application starts right now.
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« Reply #16 on: November 20, 2008, 04:43:34 04:43 »

Hallo ablo2048,

Now i go further testing on the bootloader. I'm trying to running the external code withthe /EA to Vcc. Just using hand coded to LJMP to 0x8000 address then run the external code.

I have do alot of testing. I'm trying to display a "Hello" message from the xram. Finially i found out one problem which is i can't use serial interrupt routin in my application. If using serial intterupt will not work (no display). Please can you help me to check it,

I'm using 0x8000 address at application code to do testing. I have run the debug in keil and monitor the result using Disassembly window.
1) Have to remove the STARTUP.A51 file from project (other wise the address will start at 0x0000 when debug that time and the compiler is just point at 0x0000 can't move to next address.) then only Disassembly window show the result start at C:0x8000 and the Serial Interrupt rountin look like is at C:0x8170, Excel Sheet1 result.
2)  On Excel Sheet2, When com_putchar() function is executed then the address will jump to C:0023 address. How can it jump to C:0023 address? and the compiler show error 65: no execute/read premission. Is it because i already removed STARTUP.A51 from project already? But i have set Interrupt Vector at 0x8000.

So, that serial interrupt can't work after downloaded and LJMP 0x8000. Now i'm using standard library provided from keil compiler <stadio.h> . It will working fine either the LJMP start at 0x8000 or 0x2000. Do you know why? Look like is the serial interrupt cause the problem.
 
I would like to use my code rather then using library code. It take more CODE and i'm not sure how the data store in the buffer.
If the serial interrupt got problem. Can you expected what will happen if i using Interrupt service routine in my code?

So, now i already try your method. I'm not sure how to test it. The result shown on Excel Sheet3.
Is it we have to set from
CSEG AT   00A3h
to
CSEG AT   FFFFh
?
and i'm using AT89C52 mcu. Is it possible can work?

Thank you.

« Last Edit: November 20, 2008, 05:32:56 05:32 by Help » Logged
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« Reply #17 on: November 25, 2008, 05:14:24 17:14 »

Ok, answers follow:
ad 2) putchar does write to serial port - interrupt occurs because of ti (transmit interrupt) just after character is transmitted.
Please publish Your code (or at least part of it) for bootloader and main demo application - i will try to modify both projects to work...
Yes - my vector.a51 work on 80C52 unused interrupts will be ignored.
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« Reply #18 on: November 27, 2008, 04:49:24 04:49 »

Hello pablo2048,

I have upload the my bootloader and the application sample code. Hope you can help. I realize if i add the interrupt service routine and serial interrupt it will not work already.

I have spend alot of time there already but the end still haven't success... Sad

Please help me...
Thank you.
« Last Edit: December 11, 2008, 03:50:11 03:50 by Help » Logged
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« Reply #19 on: December 11, 2008, 03:47:23 03:47 »

Please publish Your code (or at least part of it) for bootloader and main demo application - i will try to modify both projects to work...
Why pablo2048... request me to publish my code already then disappear aleady? Is it he bad faith?
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« Reply #20 on: February 06, 2009, 08:01:29 08:01 »

Hi Help,
as it seems ive been back now. Do You still need my advice in Your project?
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