why I can't use ETIMSK |= 1<<TOIE3; in ISR(USART1_RX_vect){}

[DreamCat]

I'm using MEGA128L make a little project. test ok, so I buy some new MEGA128L chip. but these new chip can't working properly.

I need use tow usart port. and a 16-bit timer...

so I start debuging.

Code:

ISR(USART1_RX_vect)
{
	cdma_received[cdma_received_cnt] = UDR1;
	cdma_received_cnt++;
	TCNT3L = 0X1F;
	TCNT3H = 0X1C;
	ETIMSK |= 1<<TOIE3;
        PORTE ^= 1<<S_LED ; // for loop test to debug
}

and the loop test for usart1:

Code:

while(1){
      uart1_sendchar(0x55); // do the loop test
      _delay_s(1); // delay 1 second
}

I want to know, Can't I use "ETIMSK |= 1<<TOIE3;" at here ? once I comment this line, test is ok, but my program need it.

I'm not using 103 mode...just different batches of chips.
I also test all function I need of MEGA128L, all is ok.

that's all...I need help.

[metal]

I am not aware of "Can't do this inside ISR", I used this way with other chips and different interrupt enable bits, but I don't understand something, You need to enable timer 3 overflow interrupt inside the ISR, Do you mean you expect the interrupt to work while you there inside the ISR, I don't think this is the case, you'r not a beginner? what is the thing that stops working when you uncomment the line? Show me something I can read better and be able to work with?

What do you mean by saying test is OK?

[DreamCat]

sorry for my simplistic description and my bad english.
I'm not a begainner, but I am now very confused.
Iit can enable another interrupt in a ISR. because this action is in end of ISR. I think it should not cause  collision.
In my case, I'm doing a loop test for USART1, there is a 470 ohm resistor connect RXD and TXD. and a loop for send a test char "0x55" in main function, once USART1 is trigger, enable Timer3 interrupt.
on my original chip it works properly, but now all is failed.

PORTE ^= 1<<S_LED  is a indicator, let me to see whether it is work or not. S_LED is PE7。

where is my wrong?

[Ichan]

If there is a different behavior of same type microcontroller but different batch, then i will try di dig into related Errata documents.

Curious, what is the use of Timer3? You try to enable it's interrupt every time a character received on Usart1? Where you disable it?

-ichan

[DreamCat]

Code:

ISR(TIMER3_OVF_vect)
{
    flag_cdma_received_complete = 1;
    ETIMSK &= ~(1<<TOIE3);
    PORTE |= 1<<S_LED ;
}

above code is ISR for timer3 overflow. as you can see there is only one flag I set.
I always use VMLAB to simulate it.. ThVortex(a add-ons auther for VMLAB) told me maybe I got mistake fuse just now.. I will try this..

but as you said, maybe different batch has some change, but I only have new chip now.. the old is set up a board and posted ...
I need to find errata documents and read...

can I say "thanks a lot indeed"?

[metal]

Did you declare "vflag_cdma_received_complete" as volatile?

In WinAVR, when you enter an ISR, it executes cli(); when you enter, it executes sei(); I know you know that, so the problem is not in your UART ISR. But I remember I used to do it manually because I was polling the interrupt flag, rather than using the interrupt it self. AVR is so much faster that sometimes I feel silly using an interrupt in some cases. If you have a copy of this code working already, as Ichan said, you need to see the errata, i will look at them tomorrow morning.

I did not mean to say you are beginner But the question mark made you misunderstand my intentions, sorry for that.

[DreamCat]

no need say sorry , you are right, I just I only better than beginner..
these two line:

Code:

        ETIMSK |= 1<<TOIE3;
        PORTE ^= 1<<S_LED ; // for loop test to debug

if I don't commnet " ETIMSK |= 1<<TOIE3;" , the next statment whill not be execute forever. even I move it to front.
"In WinAVR, when you enter an ISR, it executes cli(); when you enter, it executes sei()", this is correct, but I think "ETIMSK |= 1<<TOIE3;" only set a flag, it should not cause above case.

I also noticed this, so I add a "sei();" before "ETIMSK |= 1<<TOIE3;" in "ISR(USART1_RX_vect)", amazing! it worked now...

but..... why? 

[metal]

Try this:

ISR(USART1_RX_vect, ISR_NOBLOCK)

and remove the sei(); you added before ETIMSK |= 1<<TOIE3;

Tell me if this works or not, we will see what's really going on.


P.S. The whole sei() thing inside the ISR is dangerous in my opinion, but let us see what you get trying this way.

[DreamCat]

According  your mean. I test it. but it don't work.  I found it must  add sei();

now I'm view the related register to find what changed..

[metal]

ISR(USART1_RX_vect, ISR_NOBLOCK) means adding sei() at the beginning of the ISR routine. It should not work according to what you said: right before ETIMSK |= 1<<TOIE3;

The errata says this:

Interrupts may be lost when writing the timer registers in the asynchronous timer
The interrupt will be lost if a timer register that is synchronous timer clock is written when the
asynchronous Timer/Counter register (TCNTx) is 0x00.

Problem Fix/Workaround
Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor
0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous
Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx).

I don't know if this really applies to your case or not, but you are not writing to Timer 3 register, right?

[DreamCat]

Problem Fix/Workaround
Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor
0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous
Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx).

I didn't use these two value for Timer/Counter register.

Code:

	TCCR3A=0;
	TCCR3B = 0x01; //0 1 1 , 64 CLOCK DIV

in my case, I only set TCNT3 of timer3 and enable its overflow interrupt.

Code:

	TCNT3L = 0X1F;
	TCNT3H = 0X1C;
	ETIMSK |= 1<<TOIE3;

last exit ISR(USART1_RX_vect).


however, I will write a little code to test it, and report to here.
I think if I upload a simple test code would be more usefull

[metal]

Any news dreamcat?

[DreamCat]

Any news dreamcat?

I couldn't access here these days, may be cause by my internet sevice provider. sorry for my lately reply.

I change another register's value, and it worked properly now. the register TCCR1B.

but I maybe no chance to download it into old chip. sigh!

[DreamCat]

sorry everyone , I forgot reply this topic:

I disabled free running A/D converter when do other operator, and then all is ok.


but I still can't understand, the ISR is blocked, unless use ISR_NOBLOCK...I also tried other version of the avr-gcc...

maybe the differnce batch mega128l cause this problem.

metal give me bigest help, thank again. and thanks all.