A new design with MR2A16AVYS35 memory

[alfonsoagama]

Hello to all,

I did a design with MR2A16AVYS35 memory. But I can not write data to memory and when I read data from memory, these vary as if you were reading several directions at once.

I'm using TXB0108 x2, and SN74LVCxxxx to level translate 5v to 3.3v.

To perform a test data I need to know that memory comes from factory. All data stored in are '1 'or '0' ?

Please help me I need to identify the problem. For this, the schematic diagram attached.

Regards,

[Ganymed]

Hi alfonsoagama,

the chip enable input of the ram is low-active.
But for driving you took a OR-gate (SN74LVC1G32) on
CS- and CSM2-Signals.
I don't know your logic level of CS and CSM2
But, are you sure that the logic is correct?

[dipchip]

@Alphonsoagama

Not sure if you need R2, R3, and R5 in that circuit.
I noticed on the spec sheet for the MR2A that the read, address, and enable lines require 35ns setup time.
If your using a very fast MCU, are you waiting long enough?

--Chip

[alfonsoagama]

I'm doing a test with the NI PXI-6508 DAQ of the National Instruments. I set up the inputs to read the data from all memory addresses but I managed to obtain the data of each memory address is oscillating. Even if I read the data of only a memory address

Ganymed........... the logic level of CS and CSM2 are '0'. I'm using WE='0' for Read and WE='1' for Write

dipchip............. the setup time are 200us only for test with the  NI PXI-6508 DAQ of the National Instruments

I have two suspicions, the TXB0108 or the MRAM Memory

[dipchip]

hi,

200us is somewhat slow by today's standards, but it's still 17 times faster than the mram.
Are you waiting long enough?

--Chip

(dunno where my head was at when I typed that... it's 175 times faster!!!)

[Ganymed]

Did you have implemented a Power Up Sequence?

The MRAM is protected from write operations whenever VDD is less than VWI.
As soon as VDD exceeds VDD(min), there is a startup time of 2 ms before
read or write operations can start. This time allows memory power supplies to stabilize.

The E and W control signals should track VDD on power up to VDD- 0.2 V or VIH
(whichever is lower) and remain high for the startup time.
In most systems, this means that these signals should be pulled up with a
resistor so that signal remains high if the driving signal is Hi-Z during power up.
Any logic that drives E and W should hold the signals high with a power-on reset
signal for longer than the startup time.
During power loss or brownout where VDD goes below VWI, writes are protected and
a startup time must be observed when power returns above VDD(min).

[alfonsoagama]

dipchip....

I'm using 200us only for a test with a NI card. The problem is I can't see the correct response of the MRAM

Ganymed...

I'm using a Linear Regulator for obtain stable 3.3V to supply the MRAM and with the help of Tantalum capacitors.

Well.... I'm tkinking the problem could be in the PCB art.
The PCB has earth planes on the top and the bottom layer. The PCB has 2 layer.
Anyone have any ideas or experience in ground planes that can affect the operation of a RAM???

Thanks in advance