Title: [Req] Invite smart_techie
Post by: smart_techie on November 18, 2009, 03:36:41 15:36
| Country | INDIA | | Site | nil | | Note | -> Working with mixed signal FPGAs. Design and implemetation of RTL modules for communication Protocols.
-> Interested in ASIC Design and implementation issues, could participate in discussions and share various Design , simulation , synthesis and verification tools.
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Title: Re: [Req] Invite smart_techie
Post by: janakfun on November 18, 2009, 06:17:34 18:17
can you please brief out what communication Protocols have you implemented till date ?
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