Title: [Req] Invite Carlo
Post by: Carlo on April 14, 2015, 11:08:41 23:08
| Country | Italy | | Note | I am a DSP FPGA Design Engineer, I am responsible for architecting, implementing, & testing FPGA-based signal processing solutions for wireless communications products. I have been involved in requirements analysis, system architecting, test bench design, verification, synthesis and FPGA place and route. I have participated many projects of designing and implementing the physical layer of GSM, UMTS, LTE, WiFi wireless telecommunication protocols.
I can help members during any of the above project phases.
I have an excellent experience of:
VHDL programming,
Mentor Modelsim,
Cadence Incisive,
Xilinx ISE / Vivado,
Matlab / Simulink,
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Title: [Invited] Carlo
Post by: PeterMcMonty on April 15, 2015, 11:31:37 23:31
This member is invited by me. Registration isn't completed yet.
Note: This message sent by the system behalf of PeterMcMonty.
Title: [Registered] Carlo
Post by: Carlo on April 16, 2015, 04:59:03 16:59
Thank you for invitation. Registration is done.
Note: This message sent by the system behalf of Carlo.
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