Sonsivri

Hello All,

Does PC MotherBoards have an onboard static RAM ?
If NOT then how can the processor make any CALL,PUSH or service INTERRUPTs ?
Now a days i do not see any STATIC RAM chip on the motherboard.(Is it built into any kind of chipset)
What is going on,i do not understand how a processor can work without STATIC RAM ?

And i assume that now motherboards have started using serial SPI FLASH chips for BIOS instead of parallel one.
Does it mean that processor has special circuitry inbuilt to read and execute in place (XIP) from serial FLASH chips.

Where to get complete standard specification for the motherboard,if i want to program the BIOS chip with my own OS.


Thanks in advance
Proton

L1, L2, L3 Cache memory are Static RAM

Static RAM as opposed to dynamic RAM?


Dynamic RAM (once correctly configured and enabled during the startup) works just as well for these tasks as static RAM.

And dynamic RAM has been used on PC architectures for a very long time - As far as I can remember, from the start.

You don't need static RAM for a processor to work - at all.

Memory is memory for read operations,

For write operations, the processor doesn't know if it's static or dynamic RAM  - the timing is taken care of by a fetch unit or by the RAM itself.

What do you mean about "static" RAM?

Normal PC processor has its own internal RAM as cache and also use external DRAM for normal operation. Current BIOS is flash ROM and recent processor can normally run in native mode directly from flash address.

Also the Nonvolatile BIOS memory, it refers to a small memory on PC motherboards that is used to store BIOS settings. It uses a volatile, low-power complementary metal-oxide-semiconductor (CMOS) SRAM powered by a small battery when system power is off.

Thank you all for your responses.

praksk

"L1, L2, L3 Cache memory are Static RAM"

I think that cache memory cannot be used as a normal memory.
When the processor uses instructions like "PUSH","CALL" then it will store the pushed value or return address on to a stack allocated in normal memory.
Any access to the normal memory will go through cache.but cache itself cannot be used as a normal memory since when the cache gets filled it will have to be flushed out to the normal memory.


aplank

"Dynamic RAM (once correctly configured and enabled during the startup) works just as well for these tasks as static RAM"

In that case the very first instructions must be the one to initialize the memory controller before which there should be no "CALL","PUSH" (even it cannot enable Interrupts as well).

solutions

"You don't need static RAM for a processor to work - at all."

But the dynamic RAM needs a refresh controller and that needs to be initialized before the dynamic RAM can ever be used

robotai

"Normal PC processor has its own internal RAM as cache and also use external DRAM for normal operation. Current BIOS is flash ROM and recent processor can normally run in native mode directly from flash address."

Cache is not accessible to the processor as a RAM.It is just a way of increasing the access speed of the main mamory.
Cache is controlled by a cache controller inside the CPU.
Once the cache is full it must be flushed out to the main RAM.That is done automatically by the cache controller.
But when the cache controller tries to flush out the cache to the main memory and the main memory is not available since main memory controller has not yet been initialized then there will be a fault which might be caught by the memory manager / memory protection unit if they have been enabled beforehand.

gmua

I think the BIOS chip which is a parallel FLASH is being replaced by serial FLASH.


Thanks


Posted on: March 27, 2013, 01:50:46 01:50 - Automerged

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The computer issues BEEP even without any memory card plugged...
How is that possible...

proton

I know too little about this, so i google for "write my own pc bios" - then SuperBIOS A freeware bios for 386 intel chips (http://sourceforge.net/projects/superbios/) popping up.

If it has some use and you find about what you asked for then i will be glad to hear it.

-ichan

CPU can execute code from non volatile BIOS memory, but until external ram is verified as available, variable storage is limited to internal cpu registers.

This is why RAM trouble report is limited to beep code.

Some servers have separate cpu card with memory and Ethernet to enable out-of-band monitoring of servers, even during BIOS boot.

As my understanding, BIOS would first make basic initialization and initialize external DRAM setting in the beginning. So later process can utilize RAM properly. Before RAM been initialized, the CPU can only running in sequential instructions without CALL, PUSH commands because no stack can be setup yet.
RAM is not really needed in running simple program. That's the way how little MCU runs.

Absolutely correct.  But this is in no way unusual.  Many PC, microcomputer and embedded systems (and likely many others) work in the same way. That initial startup code to configure the memory controller is typically very small and is done very soon after the processor comes out of reset.

And also consider, many systems do not allow immediate access to SRAM after coming out of reset before a memory controller is initialised, so if SRAM is available, the same code limits can occur for that small period of time.

Power-On Self-Test (POST)

In IBM PC compatible computers, the main duties of the POST are handled by the BIOS. So even if you remove the RAM (and besides, it's "empty" to start with), the processor still has the code inside the FLASH memory that contains the BIOS to execute, and part of that code verifies the main system memory.

Posted on: March 27, 2013, 10:00:20 am - Automerged

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Yes, SPI Serial FLASH Memory have been used for some time now on new mainboards and laptops, in place of the larger PLCC and TSOP chips. They can be reprogrammed In-Circuit using SPI-ISP Programming.

But what I tried to say was, that Parallel or Serial FLASH Memory if it's used to store the BIOS of a Computer, needs a tiny (64 bytes) amount of Static RAM located on a complementary metal oxide semiconductor (CMOS) chip to store the BIOS settings.

You were doing well until you said this: "Parallel or Serial FLASH Memory if it's used to store the BIOS of a Computer, needs a tiny (64 bytes) amount of Static RAM located on a complementary metal oxide semiconductor (CMOS) chip to store the BIOS settings."

Thanks for all

f22kma

"CPU can execute code from non volatile BIOS memory, but until external ram is verified as available, variable storage is limited to internal cpu registers.

This is why RAM trouble report is limited to beep code"

But to issue beep it needs timer interrupt to be active which needs STACK in RAM

robotai

aplank

"As my understanding, BIOS would first make basic initialization and initialize external DRAM setting in the beginning. So later process can utilize RAM properly. Before RAM been initialized, the CPU can only running in sequential instructions without CALL, PUSH commands because no stack can be setup yet.
RAM is not really needed in running simple program. That's the way how little MCU runs."

But when no RAM is present it is able to produce BEEPS which needs interrupt which in turn needs STACK

gmua

"In IBM PC compatible computers, the main duties of the POST are handled by the BIOS. So even if you remove the RAM (and besides, it's "empty" to start with), the processor still has the code inside the FLASH memory that contains the BIOS to execute, and part of that code verifies the main system memory."

But how can it make any "CALL","PUSH" or interrupt service without STACK

gmua

"But what I tried to say was, that Parallel or Serial FLASH Memory if it's used to store the BIOS of a Computer, needs a tiny (64 bytes) amount of Static RAM located on a complementary metal oxide semiconductor (CMOS) chip to store the BIOS settings."

In old days BIOS was Running from parallel EPROM,then parallel FLASH.Both memories could be accessed just like any static RAM and needed no other hardware than a single chipselect.
But Serial FLASH needs commands to be given serially and data can be read serially either 1 bit,2 bits or 4 bits per clock.It needs extra hardware to access the serial FLASH.
BIOS Setting is saved in RTC


Proton

Some BIOS settings (what is usually called "CMOS data") is saved in a small area of flash memory that is often found in RTC chips. Note that it has nothing to do functionally with the RTC function per se.

besides, this is all becoming obsolete as most modern motherboards use UEFI, not BIOS anymore.

Why BEEPs need interrupt? It just keeps turning one GPIO pin to high and low repeatedly to make speaker "beep".

Yes. A beep like this does not need interrupts or stack or RAM.  It is just a simple, tight, infinite loop.

Again, nothing unique in that.

A different opinion (though never studied the PC BIOS):

In the early '80s, my power-on RAM-TEST z80 programs often used the computed call-return solution
(without any RAM, SP points to a ROM address). A simple (non-vectored) interrupt was also possible,
using other  CPU registers to save anything (eg via z80 EXX, which switch to the other register bank).

It might well pay you to run through the listings of the original IBM BIOS.

Back in the day, the bound manual for the original PC was like a bible to me. It provided an incredible insight into how a computer designed by a huge multi-national actually operated.

My copy has long since been lost. But a little searching revealled a reasonable scan.

http://www.retroarchive.org/dos/docs/ibm5160techref.pdf

The system BIOS listing is in Appendix A.

The PC also had a programmable interval timer (PIT) that could be set for a particular reload frequency, without the need for a stack or interrupts.

This could then be turned on or off to generate the beeps.

From memory, ch2 was used to drive the original PC speaker.

You'd be able to find the circuit diagrams and specifics of the speaker drive on page 1-20 of the manual I provided a link for.

Correct me if I'm wrong, but, do CPU has to configure memory manager executing BIOS code? Each DRAM module since SDRAM's have small eeprom with config stored in it. Memory manager (either in bridge or CPU unit (considering nowadays CPUs)) in hardware reads this config & sets internal registers for proper DRAM timing. CPU can override those settings in "overclocking" setup, but doesn't have to.
It simply sees the available memory since first bytes of code executed from BIOS/UEFI. Memory test stage of BIOS simply checks each memory location by write/read/compare sequence (or any other).

Couple comments,


Cache memory if properly initialized can be used as temporary storage. In fact this is what many modern bootloaders do before they have other RAM to work with.

You can set your stack there, and push and pop to your desire, or use it for variable storage that is not on stack

it's limited in space, and you have to disable flushing the cache by not assigning a window to physical memory or else you will get faults





yes, DRAM has been used for quite a while and from the processor instruction standpoint it does not really know where it is fetching opcodes/ data from - they may happen faster from different sources though.
SRAM is still faster than DDRx
It is hard to understand the performance of DDRx with great looking numbers like PC21000 or something, but keep in mind data rate != byte transfer rate since DDR is command bloated on the interface and SRAM is not


DRAM became SDRAM then DDRx, and soon to become hyper cube memory which should solve the speed problems by going to multilane and multiport 10G+ serdes i/o

almost all mainboard has no static RAM on them, but I remembered the old ASUS mainboard, there is on board static RAM.

some years ago, I disassembled a P-II CPU, there are two SRAM that made by sumsang on board.

Hi
Here are some refs about cache as ram .Coreboot (linux based open source bios replacement) does this  see http://en.wikipedia.org/wiki/Romcc
and http://www.coreboot.org/data/yhlu/cache_as_ram_lb_09142006.pdf.
This is used by uboot too, for arm http://www.linux-arm.org/LinuxBootLoader/SMPBoot.
This implies ami bios uses this technique http://www.edaboard.com/thread22441.html
Google has  a patent claiming to have invented it in 2007 (http://www.google.com/patents/US8037292). Which seems bogus as from above link i surmise that AMI did it in 2000 and it seems an obvious idea.

ps aplank have to agree about  the IBM XT technical manual .That's how to write a technical manual.